Multi-Patterning Lithography- An efficient

Photolithography technique

By
Sanka Krishna Saroja
13026D3704

Contents
Introduction
Lithography
Why multi-patterning??
Multi-patterning
Double Patterning
Mask Differentiation
Splitting Distance
Fabrication
Fabrication Steps
Advantages
Disadvantages
Conclusion
References

Introduction
Multiple patterning is a class of technologies for

manufacturing integrated circuits (ICs), developed

forphotolithographyto enhance the feature density.
The simplest case of multiple patterning isdouble

patterning, where a conventional lithography process is

enhanced to produce double the expected number of
features.
Double patterning was introduced for the32 nmhalf-pitch

node and below and is now mainly used in 10nm and

7nm technologies.

Lithography
Optical microlithography (photolithography) is a

process very similar to photographic printing.

It is used for transferring circuit patterns into the

silicon wafer.
The pattern to be replicated on the wafer is first carved

on a mask composed of quartz and chrome features.

Light passes through the clear quartz areas and is

blocked by the chrome areas.

Desired pattern is formed on the silicon wafer using an

equipment.

Lithography

(contd..)

We use an illuminator (UV

light) to shine light
through this mask
producing an image of the
pattern through the lens
system, which is
eventually projected down
into a photo resist coated
silicon wafer using a
projection system.

Figure 1. Lithography
Equipment

Why multi-patterning??
For a number of years, IC manufacturing has been

pushing the limits of optical lithography to make

silicon with features smaller than conventional
capabilities allow by employing various resolution
enhancement techniques (RET).
their resolution capabilities have fallen further and
further behind the target minimum feature size per
each advanced node.
As a result, optical lithography has finally become
unable to print shapes on silicon with a single mask
in a single pass starting at 20nm.

Multi-patterning
The solution to this problem is to use a technique

that has existed for years in the photographic

industry known as multi-patterning.
Multi-patterning means more than one mask
processes are used to manufacture each design layer.
For each design layer, the layout geometry must be
decomposed onto separate masks (or colors),
typically based on proximity to the nearest shape.
To represent a particular mask at the design level, a
"color" is associated with each layout shape to
indicate which mask is used to print the shape.

Multi-patterning
In Double
patterning the
layout is divided in
to two colors and
are placed on two
different masks.
In Triple
patterning the
layout is divided in
to three colors and
are placed on
three different

(contd..)

Figure 2. Different
Patternings

Double Patterning
The simplest case of multiple patterning isdouble

patterning, where a conventional lithography process

is enhanced to produce double the expected number
of features.
Double patterning is a technique that decomposes a
single layout into two masks in order to increase pitch
size and improve depth of focus (Df) .
The design is split over two lithography layers in a way
that the minimum pitch is relaxed with respect to the
target pitch.
The increased pitch size enables higher resolution and
better printability.

Conventional lithography versus

Double Patterning

Figure 3. Difference between conventional Lithography and

double patterning

Double Patterning

(contd..)

In Double patterning technique the layout designers

split all their routing in to two different masks called as

Mask A and Mask B.
The overall pitch between same metals will be increased
by replacing single metal with single metal two masks.
That is every metal is subdivided in to two masks.
For example if two adjacent M1 metals should have 0.64
pitch, when two masks are divided M1 mask A and M1
mask B can have only 0.32 pitch.
Due to which the routing space decreases and allows
size of the chip to decrease.

Mask Differentiation

Figure 4. Mask Differentiation

Splitting Distance

Figure 5. Double Patterning

splitting distance

DRC Colored Checks

Design rule checks for
colored metals are performed
to know the accuracy for
minimum spacing.
The adjacent figure shows
the minimum spacing for the
same mask different metals.
The DRC checks for:
Same Mask Same Metal
Spacing
Same Mask Different Metal
Spacing
Different Mask Same Metal

Figure 6. DRC Colored

Checks

Fabrication
The easiest way to implement Double

patterning in fabrication level is by transferring

the first litho step into a hard mask layer by etch
and subsequent imaging and etching of a
second photoresist layer.
This litho-etch-litho-etch approach can for
instance be achieved either by double trench or
double line patterning.

Figure 7. Litho-etch-Lithoetch process

Fabrication

(contd..)

Figure 8. Double
Patterning

Fabrication Steps
Step1: Photoresist exposed by a 45nm mask on

a silicon wafer.
The blue layer is the photoresist and the grey
layer is the silicon dioxide.

Figure 9. photo resist exposed

by a mask

Fabrication Steps

(contd..)

Step2: Etching
Etchingis used inmicrofabricationto

chemically remove layers from the surface of

awaferduring manufacturing.

Figure 10. etching

Fabrication Steps

(contd..)

Step3 : After Etching

Figure 11. after etching

Fabrication Steps

(contd..)

Step4 : Trim
photoresist trimming to reduce line width, or

photoresist reflow to reduce trench width.

The first mask patterns the array core by defining
the spacers.

Figure 12. trim

Fabrication Steps

(contd..)

Step5: A second layer sensitive to a different

photoresist is added.
Second mask is used to crop or trim the
spacers to form individual lines.
The second mask is a line cutter that separates
these into separate gates, using a second
photoresist coating.

Figure 13. layer 2 photoresist

added

Fabrication Steps

(contd..)

Step6: The most important step which shows

how the lines are doubled in this one step by

cleverly adding thinner lines along the originals
and getting rid of the originals later.
This single step reduces the pitch size from
45nm to 22nm .

Figure 14. Line doubling

Fabrication Steps

(contd..)

Step 7: The final outcome having double the

number of structures.
This conveniently avoids the serious issue of
overlay between successive exposures. The
spacer lithography technique has most
frequently been applied in patterning fins for
FinFETs.

Figure 15. Final

structure

Microscopic image
SEM(Scanning Electron Microscopy) image of a

process after double patterning .

Figure 2. SEM image of final

structure

Advantages
Can use existing process technology equipment to go to

lesser technology node.

Easy to implement.
Most cost effective technology to implement at the next
node.
Layout restrictions certainly help make Double
Patterning economically and technically more feasible.
Without multi-patterning it will be a struggle do design
at 20nm or below limiting the opportunity to take
advantage of design area and performance scaling.

Disadvantages
Yield is proportional to number of

photolithography layers so it also drops as a

result.
potential misalignment risk.
Some additional mask complexity is required in
order to connect the two layers.
Requires 2 steps of lithography where there
could be one.

Conclusion
Double Patterning Lithography is a promising

technology that is the major part of technologies

below 20nm.
Leading companies in I.C industry are using this
Multi-Patterning.
The cost of multiple mask exposures has always
been a major industrial concern. As more and more
masks are added, the cost reduction from one
technology node to the next would begin to dwindle.
A key consideration for the implementation of
multiple patterning is the tool throughput.

References
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Horak,
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Okoroanyanwu, A. Tchikoulaeva, T. Wallow, J. Chen, M. Colburn, S. Fan,
B. Haran, Y. Yin, Integration of EUV lithography in the fabrication of 22nm node devices, 2013.
[3]M. Drapeau, V. Wiaux, E. Hendrickx, S. Verhaegen, T. Machida, Double
patterning design split implementation and validation for the 32nm
node, 2009.
[4]M. Hori, T. Nagai, A. Nakamura, T. Abe, G. Wakamatsu, T. Kakizawa, Y.
Anno, M. Sugiura, S. Kusumoto, Y. Yamaguchi, T. Shimokawa, Sub-40nm
half-pitch double patterning with resist freezing process, 2010.
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Hatakeyamab, Y. Kuwahara, T. Niwa, S. Bernard, R. Gronheid, Advances
and challenges in dual-tone development process optimization, 2009.

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