By
Martin Serena, Dang Ly, Khoa Ly
Overview
(GC)
1
0
0
1
0
0
0
+
(BC)
1
+
0
+
Delegated Duties
Martin Binary to Gray Conversion,
Gray to Binary Conversion
(XOR gates)
Dang Binary/Gray Output Selection
(MUXs)
Khoa Binary Code Counter,
Parallel-to-Parallel Shift Register
(D flip-flops)
6
Method of Design
Decided on an initial load capacitance (Cin)
Partitioned the circuit into different propagation
delay times according to gate/device requirements,
and divided propagation delay times amongst the
individual gates and devices
Created the symbol and layout for out each type of
gate (XOR, MUX, NAND)
Connected gate symbols to create device symbols
Connected gate layouts to create device layouts
Connected device symbols to create circuit
schematics, and connected device layouts to create
circuit layouts
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Target Specifications
Conversion:
Binary Code to Gray Code
Gray Code to Binary Code
Simulation Results
Successfully converts binary and Gray codes
Propagation Delay
XOR (each): 0.338 nS (worst-case)
MUX (each): 0.35 nS (worst-case)
D flip-flop (each): 1.14 nS (worst-case fall time)
Wn = 3.75 m
Wn = 3 m
Wn = 10 m
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Simulation Results
Power (using the power meter)
39.94 mW
Clock Speed
200 MHz
Total Area
Gray code converter: 6.03E-4 cm2
Counter: 10.2E-4 cm2
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Block Diagram
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XOR Schematic
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XOR Symbol
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XOR Layout
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XOR Extracted
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XOR Threshold
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MUX Schematic
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MUX Symbol
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MUX Layout
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MUX Extracted
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NAND3 Schematic
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NAND3 Symbol
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NAND3 Layout
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NAND3 Extracted
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D Flip-Flop Schematic
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D Flip-Flop Symbol
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D Flip-Flop Layout
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D Flip-Flop Extracted
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Counter Schematic
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Counter Symbol
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Counter Layout
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Counter Extracted
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Power
56
Design References
CMOS Integrated Circuits
By Kang
Digital Fundamentals
Thomas Floyd
57
Conclusion
We designed and simulated a Gray code converter
that converts binary coded numbers to Gray coded
numbers and vice versa
The nmos and pmos transistor widths were greater
than 1.5 m
The power specifications were well below Watt
and a code conversion took place within 5 nS
Our target specifications were met
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