Module III

System Organization

System Organization
- How computers and their major components are interconnected and managed
at the system level.
7.1. Communication Methods
7.1.1 Basic concepts
Intrasystem communication : within a single computer, primarily buses
parallel
Intersystem communication : electrical cables and optical fibers. serial
computer network.

Buses : Physical links among the components as well as the controlling mechanism

- A single system bus handles all intrasystem communication

At any time, only two units can communicate with each other.
CPU : a bus master
M : a bus slave
I/O devices : normally a bus slave, but can be a bus master via IO processor
System bus : address, data, and control lines
The characteristics of system bus closely matches those of its host CPU.

System bus : High-speed data transfer between CPU and M.

Most IO device are slower than CPU and M.
IO controllers that perform series-to-parallel and parallel-to-series
format conversions.

Standardized IO bus : SCSI ( Small Computer System Interface )

Long-distance communication
Whereas intrasystem communication is serial by word, intersystem
communication is serial by bit due to the difficulty of synchronizing data bits
sent in parallel over long distances.
A sequence of many bits called a message is transmitted at one time.
When the pulses representing digital signal 0 and 1 are transmitted over long
distances, the pulses may become unrecognizable due to the distortion caused
by noise.
More cost-effective to embed the data in analog signals for average
quality of transmission medium.

Computer networks : Digital communication networks designed to link many

independent computers to permit sharing of computing resources.
Local area network (LAN) : private data transmission links, Ethernet
Wide area network (WAN)
Techniques for sharing the communication links
Circuit switching
Message switching : Use the intermediate servers to store messages and
subsequently forward them. Efficient utilization of links
Packet switching : To solve the problem that the short messages can be delayed
while longer messages are being transmitted, divide messages into packets of
fixed length and format, and then transmit packets from long messages
interspersed with packets from short messages.
ATM ( asynchronous transfer mode ) combines voice and data
communication using short packets that can be transmitted very fast.

The Internet : A worldwide packet-switched computer network

IMP ( Interface Message Processor )
TCP/IP ( Transmission Control Protocol / Internet Protocol )
The Internet address is 4 bytes long
more than 4 billion distinct addresses.
An Internet packet is transmitted with a header containing its most recent source
address and its final destination address, as well as a sequence number indicating
its position in the original message. An Internet package can pass through dozens
of servers before reaching the target server.

Interconnection Structures

7.1.2. Bus Control

Two key issues
timing of transfers over the bus
the process by which a unit gains access to the bus
--Synchronous communication : The bus interface circuits of both the source
and destination units are synchronized.
disadvantage : data-transfer rates are largely determined by the slowest
unit in the system.
--Asynchronous communication :
--local and long distance communication. Each item is accompanied by a
control signal that indicates its presence to the destination unit.
--The destination unit responds with another control signal to
acknowledge.

Bus interfacing :

bus driver and bus receiver

Two big advantages of tristate logic circuits

The greatly increase the fan-in and fan-out limits of bus lines, permitting
very large numbers of devices to be attached to the same line.
They support bidirectional transmission over the bus by allowing the same
bus connection to serve as an input port and as an output port at different
times.

Bus arbitration : a selection mechanism to decide among competing requests to the bus
by different units at the same time.
Daisy chaining, polling, and independent request.
Daisy-Chaining

This method involves three control signals, BUS REQUEST, BUS GRANT and BUS
BUSY.
--When any unit is required to use the bus, which enables the BUS REQUEST signal.
--bus master will respond to the request by placing a signal on BUS GRANT line.
--On receiving the BUS GRANT signal, a requesting unit enables its physical bus
connections and activates BUS BUSY for the duration of its bus activity.

--When the first unit receives the bus grant signal, it blocks further propagation.
-- The unit closest to the bus-control unit has the highest priority. Selection
priority is determined by the order in which the units are linked by the Bus
Grant lines.
--susceptible to failure.
Very few control lines and a simple fixed arbitration algorithm. A units priority
cannot be changed under program control.
Can be used with unlimited number of bus units.

 Polling method

 The Bus Grant line is replaced by poll count line.

in response to a signal on BUS REQUEST line, the bus controller proceeds to
generate a sequence of numbers on the poll count lines.
--Each unit compares to a unique address assigned to that unit.
-- When a requesting unit find s that its address matches the number on poll count lines,
then this unit activates BUS BUSY.
--Bus controller terminates the counting and the unit connects the bus.
The priority of a bus unit is determined by the position of its address in the polling
sequence. This sequence can be programmed, hence priority can be changed under
software control.
A failure in one unit needs not affect the other units.
Require more control lines ( K poll-count lines instead of one BUS GRANT line )
The number of units is limited by the addressing capability of the poll-count lines.

 Independent requesting

-- Every unit has separate BUS REQUEST and BUS GRANT lines.
--When any unit is required to use the bus, which enables its own request line and bus
controller will grant the bus according to the priority.

 Priority is determined by the bus-control unit.

-- can respond very fast to request for bus access
To control n units, require 2n BUS REQUEST and BUS GRANT lines, compared
2 lines for Daisy Chaining and log2n lines for Polling.

7.2. IO and System Control

Input Output (IO) operation refers to a data transfer between an IO device and
Memory or between an IO device and CPU.
IO control methods: depending on how CPU is involved in I/O execution, there
are four IO control methods.
1. programmed IO :
2. DMA ( Direct Memory Access ) control
3.Interrupt system
4. IO processor.

Programmed IO :
--IO operations are completely controlled by CPU.
--CPU executes programs that initiate, direct and terminate the IO operations.
--Require little or no special hardware, but causes CPU to spend a lot of time for
relatively trivial IO-related functions.
--The IO device does not have direct access to Memory.
-- A data transfer from an IO device to M requires CPU to execute several instructions,
including an input instruction to transfer the word from IO device to CPU and a store
instruction to transfer a word from CPU to M .

IO addressing : The address lines of the system bus for memory locations can also be
used to select IO devices.Two types of addressing
Memory-mapped IO :
--assign a part of main memory addresses to IO ports.
--An instruction that causes data to be fetched from or stored at address X automatically
becomes an IO instruction if X is the address of IO port.
--usual memory load and store instructions are used to transfer data words to or from
IO ports. no special IO instructions are used.

IO-mapped IO : the memory and IO address spaces are separate

--A memory-referencing instruction is different from an IO instruction.
-- A memory-referencing instruction activates memory control signals READ M
or WRITE M.
--CPU must execute separate IO instructions to activate IO control signals READ
IO and WRITE IO.
-IO instructions: Two IO instructions are used generally. IN and OUT.
--Instruction IN X causes a word to be transferred from IO port X to the CPU.
-- Instruction OUT X transfers a word from CPU to the IO port X.

DMA (Direct Memory Access) and Interrupts

The disadvantages of the programmed IO
The speed with which the CPU can service IO devices limits IO
data-transfer rates.
CPU has to spend a lot of time for IO-related functions.
DMA and interrupt systems increase the speed of IO operations by eliminating
most of the role played by CPU.

DMA
--IO device requests the CPU for IO operation with the help of an additional
controller called DMA controller.
--by receiving the DMA request from any IO device, CPU suspends its current
activity at appropriate breakpoints and grants the system bus to the DMA
controller.
-- then the DMA controller takes the control of system bus and manages the IO
operation without CPU intervention.

A DMA request by an IO device only requires CPU to grant control of the

memory bus to the requesting device at the end of any transactions involving
the use of this bus.

DMA

DMA controller contains a data buffer register IODR, an address register IOAR, and a data
counter register DC, to transfer data to or from contiguous region of memory.
--IODR is used for the temporary storage of data to be transferred.
--IOAR is used to store the base address of the memory region to be used in the data transfer.
--DC is used to store the number of words to be transferred to or from that region.
Two different ways of data transfer in DMA:
DMA block transfer : transfer a sequence of arbitrary length in a single burst. The fastest IO
data-transfer rates, but CPU may be inactive for relatively long periods.
Cycle stealing method : allows the DMA controller to use the system bus to
transfer one data word, after which it must return control of the bus to CPU.
reduced IO transfer rate, also reduced interference by DMA controller.

Process of DMA transfers

1.The CPU executes two IO instructions, which load the DMA registers IOAR and
DC with their initial values.
2.When the DMA controller is ready to transmit or receive data, it activates the
DMA REQUEST line to the CPU. The CPU waits for the next DMA breakpoint.
It then relinquishes control of the data and address lines and activates DMA
ACKNOWLEDGE. Note that DMA REQUEST and DMA ACKNOWLEDGE
are essentially BUS REQUEST and BUS GRANT lines for control of the
system bus.
3.The DMA controller now transfers data directly to or from main memory. After
a word is transferred, IOAR and DC are updated.
4.If DC has not yet reached zero but the IO device is not ready to send or receive the
next batch of data, the DMA controller releases the system bus to the CPU by
deactivating the DMA REQUEST line. The CPU responds by deactivating DMA
ACKNOWLEDGE and resuming control of the system bus.
5.If DC is decremented to zero, the DMA controller again relinquishes control of
the system bus. The CPU responds by halting the IO device or by initiating a new
DMA transfer.

Interrupts : the primary means by which IO devices obtain the services of CPU.
Interrupts significantly improve a computers IO performance by giving IO
devices direct and rapid access to CPU and by freeing CPU from the need to
check the status of its IO devices.
The basic interrupt method is to activate INTERRUPT REQUEST that
connects the interrupt source to CPU.
The process of interrupt request
1.The CPU identifies the source of the interrupt,
2.The CPU obtains the memory address of the required interrupt handler. This
address can be provided by the interrupting device along with its interrupt
request.
3.The program counter PC and other CPU status information are saved .
4.The program counter PC is loaded with the address of the interrupt handler.
Execution proceeds until a return instruction is encountered, which transfers
control back to the interrupted program

Interrupt selection : similar to bus arbitration process.

Vectored interrupts : The interrupting device supplies CPU with the starting
address or interrupt vector of the interrupt-handling program to get
the most flexible response.

7.2.3. IO Processors : execute most IO instructions

IO instruction type :
READ a block of n words from device X to memory region Y
IOP is provided with direct access to M and so can control the memory bus
when CPU does not require that bus.

Three types of instructions executed by IOP

Data-transfer instructions. These include input (read), output (write ), and

sense (read status). They cause the number of bytes in the data count field
to be transferred between the specified memory region and the previously
selected IO device.
Branch instructions. These cause the IOP to fetch the next CCW from the
specified memory address rather than from the next sequential location.
IO device control instructions. These are transmitted to the IO device and
specify functions peculiar to that device.

IOP organization : IOP and CPU share access to a common memory M via
the system bus