R

A
H

T
P
I
R
C
S
E GE
D A
E
U
R
A NG
W LA
D

N
IO

Jocelyn Flores Villaverde

Mapua Institute of Technology

HARDWARE DESCRIPTION LANGUAGE (HDL)

used to describe digital
system (microprocessor,
memory or flip-flop)
Widely used in logic
design
Verilog and VHDL
It facilitates a top-down
methodology for using
synthesis.

HARDWARE DESCRIPTION LANGUAGE (HDL)

Specification : This is the stage at
which we define what are the
important
High Level
Design parameters of
you are
This is the
the system/design
stage at which that
you define
planning
to design.
various blocks
in the design
and how
they communicate.

Fig. 1: Typical Design flow

HARDWARE DESCRIPTION LANGUAGE (HDL)

Low level design or Micro design is the

phase in which, designer describes
how coding,
each block is implemented.
In RTL
Micro Design is
converted into
Verilog/VHDL code,
using
synthesizable
constructs of the
language.

Fig. 1: Typical Design flow

HARDWARE DESCRIPTION LANGUAGE (HDL)

Simulation is the process of verifying
the functional characteristics of models
at any level of abstraction.
To test if the RTL code meets the
functional requirements of the
Specification
see if all the RTL blocks are
functionally correct.
To achieve this we need to write
testbench, which generates clk, reset
and required test
vectors.

Fig. 1: Typical Design flow

HARDWARE DESCRIPTION LANGUAGE (HDL)

Synthesis is process in which synthesis

tool like design compiler or Synplify
takes the RTL in Verilog or VHDL, target
technology, and constrains as
input and maps the RTL to target
technology primitives.
Fig. 1: Typical Design flow

HARDWARE DESCRIPTION LANGUAGE (HDL)

Implementation : JK Flip-flop
Place & Route

Fig. 1: Typical Design flow

VHDL AND VERILOG HARDWARE

DESCRIPTION LANGUAGE
VHDL (IEEE-Std 1076): A general-purpose
digital design language supported by
multiple verification and synthesis
(implementation) tools.
Verilog (IEEE-Std 1364): A general-purpose
digital design language supported by
multiple verification and synthesis tools.

VHDL AND VERILOG HARDWARE

DESCRIPTION LANGUAGE
VHDL
strongly and richly typed language
Derived from the Ada programming language, its language
requirements make it more verbose than Verilog.
The creators of VHDL emphasized semantics that were
unambiguous and designs that were easily portable from one tool to
the next.
Verilog
weakly and limited typed language
Its heritage can be traced to the C programming language and an
older HDL called Hilo.
All data types in Verilog are predefined in the language.
Verilog recognizes that all data types have a bit-level representation.
The supported data representations (excluding strings) can be mixed
freely in Verilog.

VERILOG HARDWARE DESCRIPTION

LANGUAGE
Verilog is one of the two major Hardware Description
Languages(HDL) used by hardware designers in industry and
academia.
Verilog is easier to learn and use than VHDL
Verilog HDL allows a hardware designer to designs at a high level of
abstraction such as at the architectural or behavioral level as well as
the lower implementation levels (i.e., gate and switch levels).

IMPORTANCE OF VERILOG
Digital system are highly complex.
Verilog language provides the digital designer a
software platform.
Verilog allows user to express their design with
behavioral constructs.
A program tool can convert the Verilog program
to a description that was used to make chip,
like VLSI.

LEVELS OF ABSTRACTION-1
Switch Level: Module implemented with
switches and interconnects. Lowest
level of Abstraction
Gate Level: Module implemented in terms
of logic gates like (and ,or) and
interconnection between gates

LEVELS OF ABSTRACTION-2
Dataflow Level: Module designed by
specifying dataflow. The designer is
aware of how data flows between
hardware registers and how the data
is processed in the design
Behavioral Level :Module can be
implemented in terms of the desired
design algorithm without concern for
the hardware implementation
details. Very similar to C
programming

HIERARCHICAL DESIGN
E.g.

Top
TopLevel
Level
Module
Module
Sub-Module
Sub-Module
11

Basic
BasicModule
Module Basic
BasicModule
Module
11
22

Full
FullAdder
Adder
Sub-Module
Sub-Module
22

Basic
BasicModule
Module
33

Half
HalfAdder
Adder

Half
HalfAdder
Adder

HIERARCHY

VHDL CODING FOR AND GATE

--The IEEE standard 1164 package, declares std_logic, etc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
---------------------------------- Entity Declarations ------------------------entity andgate is
module verilog_and(a, b, y);
Port( A : in std_logic;
input a, b;
B : in std_logic;
output y;
Y : out std_logic
assign y= a & b; // AND gate
);
endmodule
end andgate;
architecture Behavioral of andgate is
begin
Y<= A and B ;
end Behavioral;

MODULE- BASIC BUILDING BLOCK

A module can be an element or collection of low level design

blocks

MODULE

in1

my_module

out1
out2

in2

f
inN

outM

module my_module(out1, .., inN);

output out1, .., outM;
input in1, .., inN;
.. // declarations
.. // description of f (maybe
.. // sequential)
endmodule

Everything you write in Verilog must be inside a module

exception: compiler directives

BASIC CONCEPTS
Number is specified as
<size>'<baseformat><number>

BASIC CONCEPTS

NETS
Nets represent internal connections
between hardware elements.

REGISTERS
Registers represent data storage
elements.
In Verilog, the term register is a
variable that can hold a value.

VECTORS
Arrays of Registers and Nets

INTEGERS AND PARAMETERS

PORTS
Ports provide interface for by which a
module can communicate with its
environment

PORT CONNECTION RULES

MODULE

EXAMPLE :

EXAMPLE

CONNECTING PORTS

TYPES VERILOG CODING

Structural modeling (Gate-level)
Use predefined or user-defined primitive gates.
Interconnection of simple components
Purely structural
Dataflow modeling
Use assignment statements (assign)
Behavioral modeling
Use procedural assignment statements (always)

GATE LEVEL MODELING

When Verilog was first developed
(1984) most logic simulators operated
on netlists
Netlist : list of gates and how theyre
connected
A natural representation of a digital
logic circuit

GATE LEVEL MODELING

A logic circuit can be designed by the
use of logic gates.
Verilog supports basic logic gates as
predefined primitives. These
primitives are instantiated like
modules except that they are
predefined in Verilog and do not
need a module definition.

GATE GATE_NAME(OUT,IN1,IN2)

BUF/NOT GATES
Buf / not gates have one scalar input and one or more scalar
outputs.

DESIGN OF 4:1 MULTIPLEXER

DESIGN OF 4:1 MULTIPLEXER

M
I
S

G
N
I
T
A
L
U

VE

G
O
L
RI

HOW ARE SIMULATORS USED?

Testbench generates stimulus and
checks response
Pair is run simultaneously
Stimulus

Testbench
Result
checker

System Model
Response

WRITING TESTBENCHES
module test;
reg i0,i2,i3,i4,s1,s0;

Inputs to device under

test
Device under test

mux 4_to_1 m(out, i0, i1, i2, i3, s1, s0);

$monitor is a built-in
event driven printf

initial begin
$monitor($time,, i0 = %b i2=%b
i2=%b i3=%b s1=%b s0=%b i0, i1, i2,
Stimulus generated by
i3, s1, s0, y);
sequence of assignments
i0 = 0; i1= 0; i2 = 0;
and delays
i3 = 0; s1= 0; s0 = 0;
#10 i0 = 1;
#10 i1 = 1;
#10 i2 = 1; #10 i3 = 1; #10 s1 = 1; #10
s0= 1;

STIMULUS

4 BIT FULL ADDER

DECLARATION:

4 BIT FULL ADDER

4 BIT ADDER USING 1 BIT ADDER

TEST BENCH

TEST BENCH
initial
begin
#0 A=4b0000; B=4b0000; C_IN=1b0;
#10 A=4b0100; B=4b0011; C_IN=1b1;
#20 A=4b0011; B=4b0111; C_IN=1b1;
#30 A=4b1000; B=4b0100; C_IN=1b0;
#40 A=4b0101; B=4b0101; C_IN=1b1;
end
$initial
begin
$monitor ($time A=%b B=%b C_IN=%b SUM=
%b C_OUT=%b, A,B,C_IN,SUM,C_OUT);
end
endmodule

TESTBENCHUSING $RANDOM
module tb_ripple_carry;
parameter N=4;
reg [N-1:0]A,B;
reg C_IN;
wire [N-1:0]SUM;
wire C_OUT;
fulladd4 RCA(.a(A),.b(B),.c_in(C_IN),.sum(SUM),.c_out(COUT));
initial begin
A= 4'b0000;
B= 4'b0000;
C_IN =1'b0;
repeat(10)
input_generate(A,B,C_IN);
#45 $finish;
end

TESTBENCHUSING $RANDOM
task input_generate;
output [N-1:0]A_t,B_t;
output CIN_t;
begin
#4;
A_t = $random % 4; //Above statement will generate
Random values from -3 to +3.
B_t = $random % 4;
CIN_t =$random;
end
endtask

TESTBENCHUSING $RANDOM
task display;
input [N-1:0] A_td,B_td,SUM_td;
input CIN_td,COUT_td;
$strobe("Time =%0t \t INPUT VALUES A=%b B=%b C_IN =
%b \t OUTPUT VALUES SUM =%b C_OUT =%b",
$time,A_td,B_td,CIN_td,SUM_td,COUT_td);
endtask
always@(SUM,A,C_OUT)
$display(A,B,SUM,C_IN,C_OUT);
endmodule

DATAFLOW MODELING
In complex designs the number of gates is
very large
Currently, automated tools are used to
create a gate-level circuit from a
dataflow design description. This
process is called logic synthesis

CONTINUOUS ASSIGNMENT

RULES:
The left hand side of an assignment must
always be a scalar or vector net
It cannot be a scalar or vector register.
Continuous assignments are always active.
The assignment expression is evaluated as
soon as one of the right-hand-side
operands changes and the value is
assigned to the left-hand-side net.

Rules
The operands on the right-hand side can
be registers or nets.
Delay values can be specified for
assignments in terms of time units.
Delay values are used to control the
time when a net is assigned the
evaluated value

VERILOG CODING FOR ALL GATE

module gates(a, b, y1, y2, y3, y4, y5, y6,
y7);
input [3:0] a, b;
output [3:0] y1, y2, y3, y4, y5, y6, y7;
/* Seven different logic gates acting on four
bit busses */
assign y1= ~a;
// NOT gate
assign y2= a & b;
// AND gate
assign y3= a | b;
// OR gate
assign y4= ~(a & b);
// NAND gate
assign y5= ~(a | b);
// NOR gate
assign y6= a ^ b;
// XOR gate
assign y7= ~(a ^ b);
// XNOR gate
endmodule

EXAMPLE: HALF ADDER

A

module half_adder(S, C, A, B);

output S, C;
input A, B;

B
C

wire S, C, A, B;

A
B

Half
Half
Adder
Adder

S
C

assign S = A ^ B;
assign C = A & B;
endmodule

EXAMPLE: FULL ADDER

in1

in2

Half
Half
Adder
Adder11
ha1
ha1

I1

C I2

A
B

Half
Half
Adder
Adder
ha2
ha2

S
C

sum
I3

cin
module full_adder(sum, cout, in1, in2, cin);
output sum, cout;
input in1, in2, cin;

Module
name

wire sum, cout, in1, in2, cin;

wire I1, I2, I3;
half_adder ha1(I1, I2, in1, in2);
half_adder ha2(sum, I3, I1, cin);
assign cout = I2 || I3;
endmodule

Instance
name

cout

OPERATOR TYPES

CONDITIONAL OPERATOR

4:1 MULTIPLEXER EXAMPLE

D-LATCH / FLIP-FLOP
module latch (G, D, Q);
input G, D;
output Q;
reg Q;
always @(G or D)
begin
if (G)
Q <= D;
end
endmodule

module dff(Q, D, Clk);

output Q;
input D, Clk;
reg Q;
wire D, Clk;
always @(posedge Clk)
Q = D;
endmodule

JK FLIP-FLOP
module jkff(J, K, clk, Q);
input J, K, clk;
output Q;
reg Q;
always @(posedge clk)
if(J == 1 && K == 0)
Q <= 1;
else if(J == 0 && K == 1)
Q <= 0;
else if(J == 1 && K == 1)
Q <= ~Q;
endmodule

JK FLIP FLOP TEST BENCH

module main;
reg J,K,clk;
wire Q;
jkff jk(J,K,clk,Q);
//Module to generate clock with period 10 time units initial begin
forever begin
clk=0;
#5 clk=1;
#5 clk=0;
end
end
initial begin
#5 j=0; k=0;
#5 j=1; k=1;
#10 j=0; k=1;
#10 j=1; k=0;
end
endmodule

A COUNTER WHICH RUNS THROUGH COUNTS 0, 1, 2, 4, 9, 10,

5, 6, 8, 7, 0,

Sequence counter
module CntSeq(clk, reset,
state);
parameter n = 4;
input clk, reset;
output [n-1:0]state;
reg [n-1:0]state;
//
always @(posedge clk)
if(reset)
state = 0;
else begin

case (state)
4'b0000:state = 4'b0001;
4'b0001:state = 4'b0010;
4'b0010:state = 4'b0100;
4'b0100:state = 4'b1001;
4'b1001:state = 4'b1010;
4'b1010:state = 4'b0101;
4'b0101:state = 4'b0110;
4'b0110:state = 4'b1000;
4'b1000:state = 4'b0111;
default:state = 4'b0000;
endcase
end
endmodule

//0 -> 1
//1 -> 2
//2 -> 4
//4 -> 9
//9 -> 10
//10-> 5
//5 -> 6
//6 -> 8
//8 -> 7

8 TO 1 MULTIPLEXER : SIMULATION
WAVEFORM

6 BIT COUNTER SIMULATION WAVEFORM

6 BIT COUNTER SIMULATION RESULT

USING CADENCE LEC

LAYOUT VS SCHEMATIC

FINAL PLACEMENT AND ROUTING

THANK YOU.