6.1 REGISTERS
Register- a group of binary cells suitable for holding binary information.
Digital System
Digital System
Clock
Digital System
Digital System
Serial-Transfer Example
Timing pulse
Shift register A
Shift register B
Serial output of B
Initial value
1011
After T1
After T2
1101
1110
1001
1100
1
0
After T3
After T4
0111
1011
0110
1011
Digital System
0010
Digital System
Operation
the A register ->augend ,the
B register ->addend ,carry ->0
The SO of A and B provide a
pair of significant bits for the FA
Output Q gives the input
carry at z
The shift-right control enables
both registers and the carry flipflop.
The sum bit from S enters the
leftmost flip-flop of A
Digital System
Digital System
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Serial Adder
xi yi ci
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ci 1
0
0
0
1
0
1
1
1
si
0
1
1
0
1
0
0
0
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Serial Adder
12
Serial Adder
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JQ xy
KQ x' y ' ( x y)'
S x y Q
Digital System
Output carry
By k-map
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Digital System
15
16
LSB
Digital System
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Count sequence
A3 A2 A1 A0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
Complement A0
Complement A0
Complement A1
Complement A2
Complement A1
A0 will go from 1 to 0
and complement A1
A1 will go from 1 to 0 and
complement A2 ;
A2 will go from 1 to 0 and
complement A3
A0 will go from 1 to 0
and complement A1
Complement A3
and so on
Digital System
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Digital System
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Digital System
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Digital System
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Synchronous Counters
Digital System
Binary Counter
Up-Down Binary Counter
BCD Counter
Binary Counter with Parallel Load
Other Counter
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Digital System
23
24
TQ1 1
TQ 2 Q ' 8Q1
TQ 4 Q 2Q1
TQ8 Q8Q1 Q 4Q 2Q1
y Q8Q1
Digital System
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Digital System
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Digital System
A momentary spike
occurs in output A2 as the
count goes from 1001 to
1010 and immediately to
0000
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Digital System
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Digital System
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Digital System
30
Digital System
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Digital System
32
Digital System
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Ring Counter
Johnson Counter
Digital System
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KA B
KB 1
KC 1
Digital System
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Digital System
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Digital System
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initial fork
// test reset action load
#3 reset_b = 1;
#4 reset_b = 0;
#9 reset_b = 1;
// test parallel load
#10 I_par = 4'hA;
#10 {s1, s0} = 2'b11;
// test shift right
#30 MSB_in = 1'b0;
#30 {s1, s0} = 2'b01;
// test shift left
#80 LSB_in = 1'b1;
#80 {s1, s0} = 2'b10;
// test circulation of data
#130 {s1, s0} = 2'b11;
#140 {s1, s0} = 2'b00;
// test reset on the fly
#150 reset_b = 1'b0;
#160 reset_b = 1'b1;
#160 {s1, s0} = 2'b11;
join
endmodule
Digital System
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Digital System
initial
begin
Count = 1'b0;
Reset = 1'b1;
#4 Reset = 1'b0;
end
initial
#200 $finish;
endmodule
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Digital System
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D-FF
Digital System
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JK-FF
Digital System
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Digital System
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T-FF
Digital System
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T-FF
Digital System
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T-FF
Digital System
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Complementing flip-flop
usual for designing binary counters
T flip-flop can be obtained from a JK when inputs J and K are tied together.
If T=0 (J=K=0), the output, Q does not change.
If T=1 (J=K=1), the output, Q is complemented.
Digital System
Q = TQ+TQ
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Digital System
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Digital System
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Digital System
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Digital System
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Signal Flow
MOD Number
MOD number = 2N
, where N is the number of FFs connected in the arrangement of counter.
Frequency Division
Digital System
In any counter, the signal at the output of the last FF (i.e., the MSB)
will have a frequency equal to the input clock frequency divided by
the MOD number of the counter.
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Digital System
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Fig 7-4 Waveforms if a three-bit ripple counter illustration the effects of FF propagation
delays for different input pulse frequencies
Digital System
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Tclock N x tpd
, where N = the number of FFs.
Example.
Suppose 4-bit ripple counter using 74LS112 J-K FF
which has tpLH=16ns and tpHL= 24ns.
then the worst case tpd = tpHL = 24ns.
fmax = 1/(4x24ns) = 10.4 MHz
Digital System
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Figure 12-9: Typical Timing Diagram for Shift Register of Figure 12-8
Digital System
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