Clock Synchronization

The CL3TG receives the 8 kHz synchronization signal (TCL) extracted by the Exchange Terminal (ET) from
the incoming PCM circuit signal. The ET generates the TCL signal by means of the frame alignment time
slot in the incoming PCM circuit signal. The CL3TG contains four TCL synchronization signal inputs.
The CL3TG unit also contains a synchronization input (FS1) for an external synchronization source. The
frequency of the external synchronization source can be (N x 4 kHz, N = 2, 3, ..., 4096). The CL3TG is
automatically adapted to the frequency of the incoming signal.
The CL3TG and CLAB-S plug-in units distribute the basic timing signals in a cabinet-specific manner. The
cartridge-specific basic timing signal pairs 8M and 8k are distributed from the unit to the cabinet. One unit
contains 15 basic timing signal pairs. The cartridge-specific cabling used to distribute the basic timing
signals has not been duplicated. The active unit sends the basic timing signal to the common line.
In the BSC3i, the CL3TG plug-in units handle the clock distribution of the base cabinet (BSCC) and the
CLAB-S plug-in units in the extension cabinet (BSCD). In the TCSM3i, the CL3TG plug-in units handle the
clock distribution in the TCSA cabinet of the TCSM3i for standalone installation option, and the CLAB-S
plug-in units handle the clock distribution in the TCSA cabinet of the TCSM3i for combined BSC3i/TCSM3i
installation option.
The CL3TG is connected to the Operation and Maintenance Unit (OMU) by means of an HDLC-based
control channel (64 kbit/s). The other end of the control channel is connected to the Adapter for CCITT no.
7 (AS7-C or AS7-B) located in the control computer of the GSW2KB/GSW1KB/GSWB in the network
element. The control messages between the control computer of the GSW2KB/GSW1KB/GSWB and the
OMU are conveyed via the message bus.
The CLAB-S is connected to the Hardware Alarm Terminal (HWAT) in the OMU via an HDLC-based
asynchronous supervision bus, which is duplicated for 2n redundancy.
The CL3TG and CLAB-S normally control the changeover independently. The changeover occurs based on
the hardware alarm data passing between the halves and the supervision data conveyed on the programbased message channel. The handshaking signals between the halves are used in the changeover.
The timing signals (16.384 MHz and 8 kHz) are taken from the CL3TG to the CLAB-S along a timing signal
bus provided with redundancy. The CLAB-S receives the timing signal pair sent by the active CL3TG based
on the changeover signal passing in the bus cable. The CLAB-S plug-in units provide a wired alarm for the
supervised active incoming signal pair to the CL3TG. The CL3TG has six bus outputs. One bus usually
handles the distribution to the CLAB-S plug-in units in one cabinet row.
The units in the Clock Equipment generate their own operating voltages from the battery voltage UB.

Clock Synchronization of BSC

externally
In order to Synchronize the BSC externally, Clock inputs could be
from a Balanced port or an Unbalanced port.The equipment for
clock inputs to the BSC can be a STM (vendor- Tejas
networks/ICOMM etc) .
An output from the balanced port(Impedance 120 ohm )could be
directly used in order to Synchronize the BSC.
In case of an unbalanced port (75 ohm) a Balun could be used for
impedance matching and finally Sync the BSC.
BALUN:
A Balun is a device which converts
balanced impedance to unbalanced and
vice versa.
Fig:1 Balun

External Synchronization
cabling
(Ext SYNC interfaces at
CPRJ45)

The CPRJ45 panel accommodates two RJ45 connectors- Port

20 (symm0) and Port 21(symm1) for balanced (symmetric)
synchronization interfaces and two BNC connectors Port 27
(asymm0) and Port 28 (asymm1) for coaxial, unbalanced
interfaces.
Connections of the BSC using a Balanced Port.
For balanced port connections Port 20 and 21 are used.
Port 20 -> FS1
&
Port 21 -> FS2.

The cable to be used should have a DB

-9 connector(a cable with 4 twisted pairs)
at one end and RJ45 jack at BSC end. The
connections should be as shown in figure.

7-Green Color
8-Green white color
Frequency used:
2.048MHz

junctio
n

Cabling used for connecting external clock to

BSC.

Pin diagrams :

(Looking into a male

connector)

After ensuring a stable output of 2.048MHz ,the RJ45 end could be jacked in either Port 20 for FS1 or Port
21 for FS2 respectively .

MML commands:
1) Disconnect the existing clock inputs:
ZDRD:2M1;
ZDRD:2M2;
ZDRD:2M3;
ZDRD:2M4;
2) Connect FS1 and FS2 inputs.
ZDRC:FS1,7; (priority 7)
ZDRC:FS2,6; (priority 6)
ZDRC:2M1,5; (priority 5)
ZDRC:2M2,4; (priority 4)
ZDRC:2M3,3; (priority 3)
ZDRC:2M4,2; (priority 2)
3) Observe the Clock Inputs until it gets stabilized.
ZDRI;

Troubleshooting
If in case the Clock inputs are not getting synchronize folllowing points
could be taken into account to resolve the issue.
Re-check the frequency of the Clock input to the BSC using frequency
meter and ensure it is stable with an output of 2.048 MHz.
The Cat-5 cable (RJ45 jack) should be checked and ensure the cable
used is not faulty.
If still problem persists ,Polarity could be changed that is:
Interchange the connections at the junction .
Also, Jumper blocks W3 (FS1) and W4 (FS2) behind the Clock cartridges
should be checked. One connection is a 120 ohm balanced connection
(jumper in position 2-3) .The other connection is a 75 ohm unbalanced
connection (jumper in position 1-2).

References
S11 site documentation.
Division 4.2-Installation documents
Topic 16.10 Pg no:121
Topic 19.3 Pg no:145

Division 4.4 -Jumper setting s of the

Cartridges in BSC3i.
Topic Adaptations of External Frequency
standards with CL3TG equipment. Pg no: 19
Thank you