PIPELINE PROCESSING

-Technique of increasing processor

throughput without requiring large
amount of extra hardware.
-Applied to the design of complex
datapath units.
Intro:
-Consists of m-data processing circuits
called stages or segments.
-Each stage has a register and a
combinational datapath circuit.
-Ri serves as a buffer; it stores

PIPELINE PROCESSING
Contd..
-Ri restricts neighbors to interfere.
-A common synchronous clock is
connected to Ri in all stages.
-Each Ri receives new set of data from Di-1
except R1
-In each clock every stage transfers its
previous result to next stage.
-m-stage pipeline can process mindependent sets of data at a time.

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Contd..
-Any operation that can be decomposed into a
sequence of sub-operations of same time
complexity- can be realized by the pipeline
processor.
Example: Addition of two floating point
numbers.
4-Stage
1. Compare the exponents.
Pipelining
2. Align or equalize the mantissa.
can be
3. Add the mantissa.
done
4. Normalize the result.

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Fig: A pipelined floating point adder

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Fig: Timing of 4-stage pipelined floating point adder

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Contd..
-Let the number of operation be 4. (4 set
of data and 4 set of addition operation).
-Let the delay of each block be T;
therefore delay of overall structure is 4T
-In non-pipelined structure; completion of
4operations take 4*4T time.
-But in pipelined structure; completion of
4operations take only 4T+3 time.

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Contd..
-In general if there are N operations, the
non pipelined structure needs 4N time
but the 4-stage pipelined structure needs
N+3 time only.
-For higher values of N, the pipeline
performance is 4 times faster than the
non-pipelined one.
-4-stage pipeline speedup 4N/(N+3)

PIPELINE DESIGN
-Finding a suitable multistage algorithm
for given function.
-Steps in algorithm are split to have same
execution time to be implemented by
pipelining.
-Buffer registers should be placed
between all stages.
-Clock should be given more concern.

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FIG:
PIPELINE
D
FLOATIN
G
POINT
ADDER

PIPELINE DESIGN
-Example of multifunction pipeline;
because S3 can perform fixed point
addition by bypassing all the stages.
-It can be configured as single stage fixed
point adder or 4-stage floating point
adder.

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Design Challenges:
-The same function can be split into different
ways depending on data representation, style
of design, sharing of function between stages.
-For ex: Fourth stage of floating point adder
can be split into two stages to make 5-stage
pipeline.
-Let F is broken into m-independent steps: F1,
F2 .. Fm (m-stage pipelining)
-Let Ti be the propagation delay of datapath; TR
be the delay of buffer register.

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Contd..
-Tclk should be made greater than the
combination of maximum value of Ti and TR
Tclk = max(Ti)+TR ; i=1,2.m
-Throughput of pipelined structure is 1/T clk
-Non pipeline structures delay is

-The throughput is just the inverse of the

delay.

PIPELINE DESIGN
Contd..
-Pipeline processing performance is more
if;
Tc <