MIPS

BY ZUL
FOR HAMAZOSK

INTRODUCTION

MIPS or Microprocessor without Interlocked

Pipeline Stages is a reduced instruction set
computer (RISC) instruction set architecture

The first commercial MIPS model, R2000 was

announced in 1985.It had thirty-two 32-bit general
purpose registers, but no condition code register
which the designers considered it a potential
bottleneck.

Figure 1 shows the architecture of MIPS R2000.

=From Figure 1, a SPIM processor compose

of an integer processing unit (the CPU), and
a collection of coprocessor that perform
subsidiary tasks.
=SPIM simulates two coprocessor,
Coprocessor 0 handles traps, exceptions,
and the virtual memory system.MIPS
simulates most of the first two and entirely
omits details of the memory
system.Coprocessor 1 is the floating point
unit.SPIM simulates most aspects of this
units.

MEMORY ALLOCATION

MEMORY ALLOCATION

Based on Figure 2, system based on MIPS processors

typically divide memory into three parts:
1. Text segment :
- This holds the machine language code for
instructions in source file (user program)

2. Data segment :
- This holds the data that the program operate on. It
is divided into two parts. Static data contains data
that are statically allocated whose size does
notchange as the program access them. On top of
static data is dynamic data. This data is allocated
and deallocated by the programs executes.

3. Stack segment :
- This segment resides at the top of user address
space. In a high level language program, local
variable and parameters are pushed and popped on
the stack as the operating system expands and
shrink the stack segment toward segment toward
the data segment.

DATA ALLIGNMENT

Table 1 lists data sizes apply to MIPS chips.

TABLE 1

Table 2 shows data alignment in MIPS.

TABLE 2