and Design
5-1
Instruction
Cycle
sequence(control)
A instruction is a binary code that specifies a sequence of microoperations
Instruction codes together with data are stored in memory(=Stored Program
Concept)
The computer reads each instruction from memory and places it in a
control register. The control then interprets the binary code of the
instruction and proceeds to execute it by issuing a sequence of
microoperations.
Instruction Code :
Instruction Format
15
12 11
0
Operation Code :
Op. Code
Address
The most basic part of an instruction code
A group of bits that define such operations as add, subtract, multiply, shift, and
complement(bit 12-15 : 24 = 16 distinct operations)
Computer System Architecture
5-2
The operation is performed with the memory operand and the content of AC
Exam)
Clear AC, Increment AC,
Complement AC, ...
Store each instruction code(program) and operand (data) in 16-bit memory word
Addressing Mode
Immediate operand address :
the second part of an instruction code(address field) specifies an operand
I=0 : Direct,
I=1 : Indirect
One bit of the instruction code is used to distinguish between a direct and an indirect
address : Fig. 5-2(a)
5-3
Effective Address
The operand address in computation-type instruction or the target address in a
branch-type instruction
5-4
5-5
Accumulator(AC) : 3 Path
s2
s1
s0
M e m o r y u n it
4096 16
W r it e
LD
IN R
1
C LR
PC
LD
IN R
C LR
DR
LD
Read
AR
A d d re s s
Bus
IN R
3
C LR
AC
LD
IN R
C LR
IN P R
IR
TR
LD
LD
IN R
C LR
O UTR
LD
C lo c k
1 6 - b it c o m m o n b u s
5-6
I=0 : Direct,
I=1 : Indirect
15 14
12
I Opcode
Address
Register-reference instruction
7xxx (7800 ~ 7001) : CLA, CMA, .
15 14
12
11
0 1 1 1
Register Operation
Input-Output instruction
Fxxx(F800 ~ F040) : INP, OUT, ION, SKI, .
15 14
12
1 1 1 1
11
Symbol
A ND
A DD
LDA
STA
BUN
BSA
ISZ
CLA
CLE
CMS
CME
CIR
CIL
INC
SPA
SNA
SZA
SZE
HLT
INP
OUT
SKI
SKO
ION
IOF
Hex Code
I=0 I=1
0x x x 8x xx
1x x x 9x xx
2x x x Ax x x
3x x x Bx x x
4x x x Cx x x
5x x x Dx x x
6x x x Ex x x
7800
7400
7200
7100
7080
7040
7020
7010
7008
7004
7002
7001
F800
F400
F200
F100
F080
F040
Description
A nd memory w ord to A C
A dd memory w ord to A C
Load memory w ord to A C
Store content of A C in memory
Branch unconditionally
Branch and Save return address
Increment and skip if z ero
Clear A C
Clear E
Complement A C
Comp e
m
Circulate right A C and E
Circulate left AC and E
Increment AC
Skip nex t instruction if A C positive
Skip nex t instruction if A C negativ e
Skip nex t instruction if A C z ero
Skip nex t instruction if E is 0
Halt computer
Input character to A C
Output character from AC
Skip on input flag
Skip on output flag
Interrup
Inter
I/O Operation
5-7
5-8
11 - 0
3 8
decoder
7 6 5 4 3 2 1 0
O t h e r in p u t s
D0
D
12
.
.
.
C o n tro l
l o g ic
g a te s
C o n tro l
o u tp u ts
T 15
T
.
.
.
13
15 14
.
.
.
14
4 16
decoder
4 - b it
seq uenc e
c o u n te r
(S C )
.
.
.
15
1 0
In c re m e n t( IN R )
C le a r ( C L R )
C lo c k
5-9
Instruction Cycle
1) Instruction Fetch from Memory
2) Instruction Decode
3) Read Effective Address(if indirect addressing mode)
4) Instruction Execution
5) Go to step 1) : Next Instruction[PC + 1]
Instruction Fetch : T0, T1(Fig. 5-8)
Continue
indefinitely
unless HALT
instruction is
encountered
T0 : AR PC
T1 : IR M [ AR], PC PC 1
T0 = 1
T0 : AR PC
1) Place the content of PC onto the bus by making the bus selection inputs S 2S1S0=010
2) Transfer the content of the bus to AR by enabling the LD input of AR
Computer System Architecture
5-10
T1 = 1
T1 : IR M [ AR], PC PC 1
Instruction Decode : T2
T1=1
Op.code
s2
T0=1
s1
Address Di/Indirect
IR (12 14)
D7=1
Register(I=0)
A d d re s s
R ead
D 7IT3(Execute)
Read effective
Address
I/O
(I=1)
D 7IT3 (Execute)
D7=0 : Memory Ref. Indirect(I=1)
D 7IT3( AR M [ AR
) ]
Direct (I=0)
nothing in T 3
Register I/O T3 Memory Ref.
T3 Operand effective address
MM ee mm oo rryy uu nn i itt
Bus
s0
0
1
0
AR
PC
LD
IN R
IR
LD
C lo c k
C om m on bus
1
1
1
5-11
3X8
Decoder
D7 : Register or I/O = 1
PC
T1
IR
IR(12,13,14)
= 111
T2
Instruction(Tab. 5-4)
( R e g is te r o r I/O ) = 1
( I/O ) = 1
D0T4 : DR M [ AR ]
PC +1
D e c o d e o p e r a t io n c o d e in I R ( 1 2 - 1 4 )
AR
IR ( 0 - 1 1 ) , I
I( 1 5 )
D6 - D0 : 7 Memory Ref.
AND to AC
M [AR], PC
0 = ( r e g is te r)
0 = ( M e m o ry - re fe re n c e
( in d ir e c t ) = 1
D0T5 : AC AC DR , SC 0
T3
E x e c u te
in p u t- o u tp u t
in s tr u c tio n
SC
0
ADD to AC
D1T4 : DR M [ AR ]
T3
E x e c u te
r e g is t e r - r e f e r e n c e
in s tru c tio n
SC
0
D1T5 : AC AC DR , E Cout , SC 0
0 = ( d ire c t)
T3
AR
M [AR]
T3
N o th in g
E x e c u te
m e m o ry - re fe re n c e
in s tr u c tio n
SC
0
5-12
PC = 10
PC = 21
D5T4 : M [ AR] PC , AR AR 1
D5T5 : PC AR, SC 0
0
BSA 135
next instruction
BUN 135
D6T4 : DR M [ AR ]
D6T5 : DR DR 1
D6T6 : M [ AR ] DR , if ( DR 0) then ( PC PC 1), SC 0
5-13
1 : Ready
0 : Not ready
5-14
In s tr u c tio n c y c le
In te r r u p t c y c le
=1
F e tc h a n d d e c o d e
in s t r u c t io n
S to r e r e tu r n a d d r e s s
in lo c a t io n 0
M [ 0]
PC
=0
IE N
E x e c u te
in s t r u c t io n
=1
=1
B r a n c h to lo c a tio n 1
PC
1
FG I
=0
=0
=1
R = 0 : instruction cycle
R = 1 : Instruction cycle
IE N
R
FG O
0
0
=0
0
PC = 1
The condition
for R = 1
' ' '
Save Return
Address(PC) at 0
Jump to 1(PC=1)
Interrupt
Here
256(return address)
0
BUN 1120
Main Program
255
256
RT0 : AR 0, TR PC
RT1 : M [ AR ] TR, PC 0
RT2 : PC PC 1, IEN 0, R 0, SC 0
Interrupt
1120
Service Routine
1
BUN
5-15
5-16
Register Control : AR
Control inputs of AR : LD, INR, CLR
Find all the statements that change the AR
AR ?
in Tab. 5-6
R' T0 : AR PC
Control functions
R' T1 : AR IR (0 11)
LD( AR) R' T0 R' T1 D7 ' IT3 D7 ' IT3 : AR M [ AR]
CLR( AR) RT0
RT0 : AR 0
INR ( AR) D5T4
12
F ro m B u s
LD
D '7
I
T3
C lo c k
R
D
T4
D5T4 : AR AR 1
RT2 : IEN 0
C LR
T0
? M [ AR]
pB6 : IEN 0
IN R
To Bus
T2
pB7 : IEN 1
12
AR
D '7
I
T3
J
0
1
KQ(t+1)
1
0
0
1
B7
SET
C lo c k
B6
IE N
C LR
R
T2
5-17
Bus Control
Encoder for Bus Selection : Tab. 5-7
S 0 = x 1 + x 3 + x5 + x7
S 1 = x 2 + x 3 + x6 + x7
S 0 = x 4 + x 5 + x5 + x7
x1 = 1 :
Bus AR Find ? AR
D4T4 : PC AR
D5T5 : PC AR
Control Function :
x2 = 1 :
x1 D4T4 D5T5
Bus PC Find ? PC
x1
x2
x3
x4
x5
x6
x7
S0
Encoder
S1
S2
Multiplexer
Bus Select
Input
x7 = 1 :
Same Bus
as Memory
Read
Memory
Control Function :
Find ? M [ AR]
5-18
Fig. 5-21
Fig. 2-11
16
16
F ro m D R
8
F r o m IN P R
Adder and
lo g ic
c ir c u it
A c c u m u la t o r
r e g is te r
(A C )
16
LD
Fig. 5-20
IN R
16
To Bus
C L R C lo c k
C o n tro l
g a te s
5-19
AND
16
AC
LD
IN R
C LR
To Bus
C lo c k
T5
D0T5 : AC AC DR
D1T5 : AC AC DR
D2T5 : AC DR
pB11 : AC (0 7) INPR
16
ADD
DR
T5
LD
rB9 : AC AC
IN P R
B 11
r
CLR
rB5 : AC AC 1
INR
C O M
SHR
SHL
IN C
C LR
B 11
5-20
A C ( i)
( O u tp u t o f O R g a te in F ig . 5 - 2 0 )
AND
C
ADD
FA
C
i+ 1
F ro m
IN P R
b it ( i)
J
0
1
LD
Ii ( F ig . 2 - 1 1 )
DR
KQ(t+1)
1
0
0
1
A C ( i)
IN P R
C lo c k
C O M
SHR
* Fig. 2-11
Increment, Clear,
Count
A C ( i+ 1 )
SHL
A C ( i- 1 )
Mano Machine
Integration !
5-21
Due Date : 1