Electronics in

Mechatronics System
Zulfakar Bin Aspar
Faculty of Electrical Engineering (FKE)
zulfakar@fke.utm.my
019-7311350
 Module 1
BHM4402
Electronics in
Mechatronics System

INTRODUCTION
 3
COURSE OUTLINE
AIM:
This course introduces storage of digital information,
transmission of signals, programmable memories such as
EEPROM or FPGA, power electronics, control of electrical
motors and aspects of EMC and assessing the reliability of
electronic devices.

LEARNING OUTCOME:
1. Apply different concepts for transmitting and storing
digital information - FPGA
2. Install electrical circuits for power electronics and to adapt
these to changing conditions.
3. Assess the reliability of electronic devices.
 4
COURSE OUTLINE (2)
Whats in this course:
Learning to use Altera Quartus II - (Xilinx)
FPGA implementation
EMC/EMF in circuit reliability
Hardware interfacing for control
Pre-Requisites
Digital System knowledge:
Number representation, coding, registers, state machines
Realization of simple logic circuits
Integrated circuit technologies
Designing with MSI components
Flip-Flops
Counters and sequential MSI components
Circuit theory
Electronic circuit theory
 5
Material
Lecture notes
Will be posted in
Dropbox
Must read before class
Find material before
class
Marks for asking in
class
Textbooks
In progress
 6
THIS SEMESTER APPROACH
o Tests 30%
2 out of 3
Practical test is an option
o Lab Project 20%
10% - demonstration of FPGA basic skills
10% - demonstration of electronic design skills
Simulation only
o Main Project 50%
Combination of FPGA and electronic circuits
Control application
Minimum one presentation
6
 7
COURSE POLICY
Attendance is compulsory.
You are responsible for whatever is taught in the
lecture. If you miss a class, it is your responsibility
to find out about assignment, tests and exam from
DROPBOX AND EMAILS.
Punctuality is expected.
Makeup tests or evaluation will not be given except
in the case of life and death!
These reasons are not entertained:
Already bought ticket: test/evaluation can be in short notice
as if you work
Only official letters are acceptable
You are encouraged to collaborate (not copy) on
assignment problems with your "study buddies.
 Plastic
Chip case
Module 1

Pins

Introduction
 SEE4243
Digital Systems
Week 4:
Programmable Logic
Devices (PLDs)
 Problems by Using Basic 10
Gates
o Many components on PCB:
o As no. of components rise, nodes
interconnection complexity grow
exponentially
o Growth in interconnection will cause
increase in interference, PCB size,
PCB design cost, and manufacturing
time
Solution: use PLDs
4-10
 Types of Programmable Logic 11
Devices
o SPLDs (Simple Programmable Logic Devices)
ROM (Read-Only Memory)
PLA (Programmable Logic Array)
PAL (Programmable Array Logic)
GAL (Generic Array Logic)

Device AND-array OR-array

PROM Fixed Programmable
PLA Programmable Programmable
PAL Programmable Fixed
GAL Programmable Fixed

o CPLD (Complex Programmable Logic Device)

o FPGA (Field-Programmable Gate Array)
4-11
 Basic Configuration of Three Simple
PLDs

4-12
 Symbol Equivalent

x x x
x
x x

Buffer or inverter

4-13
 AND PLD Notation
Programming is done by blowing the fuse

a b
a abc c abc
b
c

AND gate before programming

a b
a c
ab ab
b
c

AND gate after programming

4-14
 OR PLD Notation
Programming is done by blowing the fuse

a b c
a a+b+c a+b+c
b
c

OR gate before programming

a b
a c
a+b a+b
b
c

OR gate after programming

4-15
 PROM Notation
X0
X1 Fixed
AND array
Xn-1 (decoder)

F1
F2
Programmable
OR array
Fm-1

A virgin PLA has X at all junctions in OR array

4-16
 PROM Implementation
X0
X1
X2

X2 X1 X0 F1 F2
0 0 0 1 0
0 0 1 1 1
F1
0 1 0 1 1
F2
0 1 1 0 0
1 0 0 0 1
1 0 1 1 0
1 1 0 0 1
1 1 1 1 0

4-17
 PLA Notation
X0
X1 Programmable
AND array
Xn-1 (decoder)

F1
F2
Programmable
OR array
Fm-1

A virgin PLA has X at all AND and OR junctions

4-18
 PLA Implementation X1X0
X2
00 01 11 10
X2 X1 X0 F1 F2 0
1 1 0 1
0 0 0 1 0
1
0 1 1 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 0 F1 = X2 X0 + X2 X0 + X2 X1 X0
1 0 0 0 1
1 0 1 1 0 X1X0 reused
X2
1 1 0 0 1 00 01 11 10
1 1 1 1 0 0
0 1 0 1
1
1 0 0 1

F2 = X2 X0 + X1 X0 + X2 X1 X0

4-19
 PLA Implementation
Try to implement both functions using minimum
number of total terms (product sharing). Hence F1
has 3-input term.
X0
X1
X2

F1
F2

F1 = X2 X0 + X2 X0 + X2 X1 X0 F2 = X2 X1 X0 + X2 X0 + X1 X0
4-20
 PAL Notation
X0
X1 Programmable
AND array
Xn-1 (decoder)

F1
F2
Fixed
OR array
Fm-1

Each AND gate is permanently connected to a certain OR gate

4-21
 PAL Implementation X1X0
X2
00 01 11 10
x2 x1 x0 F1 F2 0
1 1 0 1
0 0 0 1 0
1
0 0 1 1 1
0 1 1 0
0 1 0 1 1
0 1 1 0 0 F1 = X2 X0 + X2 X0 + X1 X0
1 0 0 0 1
1 0 1 1 0 X1X0
X2
1 1 0 0 1 00 01 11 10
1 1 1 1 0 0
0 1 0 1
1
1 0 0 1

F2 = X2 X1 X0 + X2 X0 + X1 X0

4-22
 PAL Implementation
X0
X1
X2

F1
F2
unused

F1 = X2 X0 + X2 X0 + X1 X0 F2 = X2 X1 X0 + X2 X0 + X1 X0

4-23
 A Real PAL: 16L8
o Theres 64 AND gates
o Each AND gate can have 32
inputs (16 variables &
complements)
o Theres 8 outputs
o Dont count the I/O pins!
o Three common output
configs:
L = pure combinational
R = registered
V = macrocell

16 L 8
sixteen inputs eight outputs

output configuration

4-24
 25
Sequential PALs

o16R8
oNotice 8 flip-flops
at output

4-25
 GAL (Generic Array Logic)
o GAL can emulate a number of PALs
o No need for PAL anymore!

PAL GAL
Device Fuse Electrically erasable cell
technology
Reconfigurability One-time Erasable, reprogrammable
programmable
I/O Fixed function Selectable: input/output,
combinational/registered

Oh, by the way

GAL is trademark of Lattice Semiconductor: example
GAL22V10
Universal PAL is the trademark of Vantis: example
PALCE22V10 (but its the same thing!)
4-26
 27
GAL16V8
oEach output is
programmable as
combinational or
registered
oAlso has
programmable
output polarity

4-27
 OLMC = Output Logic 28
o OLMC = Output Macrocell
Logic Macrocell
o Simplified, equivalent circuits:

4-28
 Simplified GAL
Representation
x0
x1
x2

OLMC

OLMC

OLMC

4-29
 PALCE22V10 Organization
30

4-30
 PALCE22V10 Macrocell

4-31
 32
Problems Using SPLD
o Current trend is
Increasing gate count
Increase design complexity
Requirement for smaller size due to lower cost, lower power
and higher reliability
Fast prototyping for quick design verification
PROM, PLA and PAL not used much except in small designs!

o Solution:
CPLD for intermediate complexity
FPGA for very complex designs (up to millions of gates)

4-32
 33
Advantages of CPLDs
o Reduced circuit board space
utilization,
A 44-pin CPLD is and significant cost
equivalent to 600
savings
gates

Some CPLDs have gate

equivalents in the
millions and over 1000
pins.
Universal inventory, as one IC can be
programmed for various applications

4-33
 34
Advantages of CPLDs
o Easiest to modify
Modify the software to modify the hardware

o Easy to duplicate

Design

o Direct entry of conceptual design into functional

circuit
Streamlined design to prototype process

Design
idea

4-34
 35
Advantages of CPLDs
o Reprogrammability
CPLD can be reprogrammed hundreds of times.

Design 1

Design 2

Design 3

o Number of I/Os
CPLDs have large amounts of programmable input/output
contacts.

4-35
 36
Advantages of CPLDs
o Software and Language
Manufacturers of CPLDs supply design software (basic
software, like the Max II Plus +, is a free download)
VHDL is a standards-based language that most manufacturers
conform to.

o Simple Interface
Devices can be interfaced directly to a computer with a serial
or USB connection .

o In-circuit modifications
With the proper interface connections, the CPLD logic can be
edited in-circuit.

o Transportable design
As a designer you may easily exchange your designs and
4-36
design modifications (email, CD, web site, etc).
 CPLDs and FPGAs
CPLD FPGA
Complex Programmable Logic Device
Field-Programmable Gate Array

Architecture PAL/22V10-like Gate array-like

More Combinational More Registers + RAM
Density Low-to-medium Medium-to-high
0.5-10K logic gates 1K to 1M system gates
Performance Predictable timing Application dependent
Up to 250 MHz today Up to 150 MHz today
Interconnect Crossbar Switch Incremental

4-37
 38
CPLDs vs. FPGAs
o CPLD
architecture

o Small number of largish

PLDs (e.g., 36V18) on a single chip
o Programmable
4-38 interconnect between PLDs
 39
CPLD
o Defined by microcells
o Each microcells consists of
AND
OR
Multiplexer
Flip-flop

4-39
Xilinx 9500-series macrocell (18 per40
Set control FB)
Programmable
inversion or XOR
product term

Up to 5
product
terms
Global clock or
product-term
clock
Reset control

OE control
4-40
 41
FPGA architecture

o Much larger number of

smaller programmable logic blocks.
Xilinx calls them CLB (Configurable Logic Block)
Altera calls them LAB (Logic Array Block) and EAB (Embedded Array Block)
o Embedded in a sea of lots and lots
4-41
of programmable interconnect.
 42
Configurable Logic Block
o Two flip-flops per CLB, plus two per I/O cell.
o 25 gates per CLB if used for logic.
o 32 bits of RAM per CLB if not used for logic.
o All of this is valid only if your design has a perfect fit.

4-42
 Configurable Logic Block
(CLB)

4-43
 Input/Output Block (IOB)

4-44
 Interconnection Detail

connections
controlled by
RAM bits

4-45
 Design Flow
Design Entry in schematic and/or HDL
(ABEL, VHDL, Verilog). Vendors include
1 Altera, Synopsys, Aldec (Xilinx
Foundation), Mentor, Cadence, Viewlogic,
etc.

Implementation includes Placement

2 & Routing. Also, analyze timing, view
layout, and more.

Download directly to the

hardware device(s) with
almost unlimited reconfigurations!! 3

XC4000 XC4000 XC4000

4-46
 Development Process
Design Specification

Design Entry
Design Modification
Design Compilation

Functional Verification

Timing Verification

Device Programming

In- System Verification

Sytem Production

4-47
 Problems common to CPLDs and 48
FPGAs
o Pin locking
Small changes, and certainly large ones, can cause
the fitter to pick a different allocation of I/O blocks
and pinout.
Locking too early may make the resulting circuit
slower or not fit at all.
o Running out of resources
Design may blow up if it doesnt all fit on a single
device.
On-chip interconnect resources are much richer than
off-chip; e.g., barrel-shifter example.
Larger devices are exponentially more expensive.

4-48
 49

Q&A
 50
Example 50

20102011-I
 51
A Review on Control
o Open loop system
System run without intervention regardless
of the output status
System only response to the predetermine
inputs
o Close loop system
System run with possible intervention
based on output status
System can be interrupted and change
direction at any time by the user
 52
WHY NEEDED
o Sensors, Transducers and Actuators
Feedback to the system for future
response
Useful information and response to the
user
Safety by avoiding hazardous contacts
Complementary to undetected by
human senses
AUTOMATE the process to increase
productivity
 53
AUTO FEEDING MACHINE
 54
DATA ACQUISITION
o Icing on the cake, add value to
system, analysis for future use
o improvement, remote monitoring and
control, quick response
o 1. Data collection in memory
o 2. Large data using database
o 3. Human Machine Interface
o 4. SCADA