WICHIP

CHIP DESIGN FLOW

1
Design flow

2
Engineering
ideas

Evolution of: Design Methodology

Historical Technology

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Engineering
ideas

Transition of: SoC Design Methodology

From Area-Driven To Timing-Driven Design

From Block-Based To Platform-Based Design

SRAM
uP Core
Flash
SRAM
uP Core
ROM SRAM FIFO
MPEG
Logic ROM Serial

Logic Logic USB MMC I/F Logic

Soft I/F IP

ADD TDD BBD PBD

Design Methodology
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Engineering
ideas

Reuse : The Key to SoC Design

Virtual Component
Reuse
Socketized Functions for
Core Reuse Plug & Play Integration

Predictable, Preverified Decision-Making:

Core Functions Qualified IP ?
Source Reuse Standard Compliant ?
Adequate testbench: (VSI, etc.,)
Functional Starting
Personal Reuse Points for Block Design Executable Spec. Core Protocol
Qualification : (OCP, Washbone, etc.,)
Designer-Specific Documented Spec. RTL Linting, Interface-Based
Reuse Practices Feedback for Update Coverage Analyzer TestBench
Block Design :
Who's original designer ?
Spec and Constraint
ADD TDD BBD PBD

Opportunistic IP Reuse Planned IP Reuse

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Engineering
ideas

System-On-Chip Design Flow

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Engineering
ideas

The System Design Process

1. System Requirement
2. Model Refinement and
test
3. Hardware/Software
Partitioning
4. Block Specification
5. System Behavioral
Model and Co-
Simulation

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Engineering
ideas

Specification Problem

First part of design process

Most crucial, Challenging, Lengthy phase of Project

Clear, Complete, Consistent Spec.

Ready to RTL Coding, but Difficult!

Spec. Documentation
Less cost when early phase of design

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Engineering
ideas

Purpose of Specification
Specification for Integration
Functional/Physical/ Design requirements
The Block diagram
Interfaces to external system
Manufacturing test methodology
Software model
Software requirements
Specification for Block Design
Algorithm Spec
Interface Spec
Authoring Guide
Test Spec Lint & Coverage
Synthesis Constraints
Verification Environment, Tools Used

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Engineering
ideas

Types of Specifications

Written in Natural Language

Traditional, Ambiguous, Incompleteness, Erroneous

Formal Specification
Desired characteristic (functionality, timing, power, area,), independent
to implementation
Not widely used, important research topic

Executable Specification
Description of Functional behavior
Parallel with RTL Model in the TestBench
Fast Feed-Back
Higher Level : C/C++(SpecC, SystemC), SDL, etc.,
Lower Level : VerilogHDL, VHDL,

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Engineering
ideas

Flow for Top-Level Block Design

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Engineering
ideas

Block Design Process

Specification and
Partitioning
Subblock Specification
and Design
Testbench
Development
Timing Check
Integration
Productization

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Engineering
ideas

Flow for Subblock Design

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From FPGA to ASIC:
Design Flow

14
Engineering
ideas

Front-End Procedure

Overall procedure

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Engineering
ideas

Back-End Procedure

Overall procedure

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Engineering
ideas

Back-End Procedure

Overall procedure (contd)

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Design Example 1

18
Engineering
ideas

Specification & Block Design

802.11a Transmitter

plcp_tx_data
pulse_shape_re

plcp_data_vld
conv pilot guardtime data pulse
scrambler interleaver mapper ifft pulse_shape_im
encoder insertion insertion selection shaping
plcp sig_vld

pulse_shape_vld
plcp_tail_vld

clk

preamble
rst_n tx_control
generator

BLOCK 1 BLOCK 2

Transmitter top block design

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Engineering
ideas

Specification & Block Design: Transmitter Top Block

Block Delays

interrup t sig nal

plcp_tx

724 clo ck SIG NA L start

scrambler
1 c loc k

conv_enco der

243 clo ck

interleaver
51 clock / 99 c lo c k / 195 c loc k 241 c loc k

mapp er
51 c lock

p ilot_insertion
c loc k
142 c loc k

ifft
49 c lo ck

guardtime_insertion
3 c lo c k

data_selection

p reamble_start

Total delay: 726 clks

(~16us)
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Engineering
ideas

Specification & Block Design: Transmitter Sub-Block

Scrambler
- Algorithm Description: c lk
rst_n sig _out_vld
sig _in_vld
data_out_vld
data_in_vld Sc rambler
tail_vld
out_data
in_data

S x x7 x4 1

Name Width Dir Description

Clk 1 I Clock (rising edge)

Rst 1 I Reset input (Active Low)

sig_in_vld 1 I Signal filed input valid

(Active High)

data_in_vld 1 I Data filed input valid

(Active High)

tail_vld 1 I Tail bits valid signal (Active

High)

in_data 1 I Data Input

sig_out_vld 1 O Signal out valid (Active

High)

data_out_vld 1 O Data out valid (Active High)

out_data 1 O Scrambled data output

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Engineering
ideas

Specification & Block Design: Transmitter Sub-Block

Scrambler: Timing Analysis

1 cycle : 240 clk

clk

rst_n

sig_in_vld

data_in_vld

tail_vld

in_data

out_sig_vld

out_data_vld

out_data

out_vld
0 0 0 0 0 0
out_data

sc rambled
sc rambled data tail bits(all z eros) data

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Engineering
ideas

Specification & Block Design: Receiver Top Block

802.11a Receiver

g uardtime
sync fft pilot_extract rx_buffer equalizer demapper deinterleaver viterbi descrambler
remove

plcp_rx

rx_c ontrol

BLOCK 1 BLOCK 2

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Engineering
ideas

Specification & Block Design: Receiver Top Block

Timing Analysis

sync out vld

sync

242 clock SIG NAL start

guard time
remover
142 clock
fft

65 clock
pilot_extract
2 clock

rx_buffer
51 clock

demapper
1 clock

deinterleaver

110 clock
viterbi

1 clock
descram

48 clock

plcp_rx

662 clock

Total delay: 662 clks

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Engineering
ideas

Specification & Block Design: Receiver Top Block

Synchronizer: Block
Diagram
Name wid Dir Description
t
h
clk 1 I Clock (60 MHz)
rst_n 1 I Reset input (Active Low)
en 1 1 Block enable
in_re 16 I Received data from ADC(real)
in_im 16 I Received data from
ADC(imaginary)
fine_clk 1 O tracking clock(20 MHz)
fine_vld 1 O Out valid
fine_re 16 O phase compensation signal(real)
fine_im 16 O phase compensation
signal(imaginary)

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Engineering
ideas

Specification & Block Design: Receiver Top Block

Synchronizer: Timing
Analysis

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Verification

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Engineering
ideas

RTL Simulation & Verification

Transmitter Top Block

Input data from PLCP Transmission data over the air

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Engineering
ideas

RTL Simulation & Verification: Transmitter Top Block

Modulator Sub-Block

BPSK QPSK 16QAM

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Engineering
ideas

RTL Simulation & Verification: Receiver Top Block

De-modulator Sub-Block

BPSK QPSK 16QAM

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Engineering
ideas

RTL Simulation & Verification

Input
data

Output
data
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Engineering
ideas

Gate Level Simulation & Verification

Transmitter Top Block Synthesis

Mapping to part: xc2v6000bf957-6

Global buffer usage summary: BUFGs + BUFGPs:
of 8 (12%)
Mapping Summary: Total LUTs: 8149 (12%)
Mapper successful!
Process took 279.406 seconds realtime, 279.406
seconds cputime
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Engineering
ideas

Gate Level Simulation & Verification

Transmitter top block gate level simulation and
verification
Re-simulated with netlist .vm file (output of synthesis
process, using Synplify Pro)
After debugging and retiming:
Library used: UNISIMS_VER, ROM and RAM modules

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Engineering
ideas

Gate Level Simulation & Verification

Transmitter subblock gate
level synthesis
Mapper (Modulator) synthesis
result
Synthesis result report
### END TIMING REPORT ###
Resource Usage Report for mapper
Mapping to part: xcv1000ebg560-6
Cell usage:
MUXCY_L 23 uses
XORCY 25 uses
FDRE 299 uses
FDR 2 uses
FDS 11 uses
FDSE 1 use
MUXF5 552 uses
FD 8 uses
FDE 315 uses
BUF 14 uses
GND 1 use
VCC 1 use
BUFG 1 use
I/O Register bits: 0
Register bits not including I/Os: 636
(2%)
Global buffer usage summary: BUFGs
+ BUFGPs: 1 of 4 (25%)
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Mapping Summary: Total LUTs: 2665
Engineering
ideas

Gate Level Simulation & Verification

Transmitter subblock gate level simulation and
verification
Mapper, resimulated with netlist .vm file (output of synthesis
process, using Synplify Pro)
After debugging and retiming:
Library used: UNISIMS_VER, ROM and RAM modules

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Engineering
ideas

Gate Level Simulation & Verification

Receiver Top Block
Synthesis

Mapping to part: xc2v6000bf957-6

Global buffer usage summary: BUFGs + BUFGPs: 2
of 8 (25%)
Mapping Summary: Total LUTs: 13488 (19%)
Mapper successful!
Process took 664.656 seconds realtime, 664.656
seconds cputime
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Engineering
ideas

Gate Level Simulation & Verification

Receiver top block gate level simulation and
verification
Resimulated with netlist .vm file (output of synthesis
process, using Synplify Pro)
After debugging and retiming:
Library used: UNISIMS_VER, ROM and RAM modules

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Engineering
ideas

Gate Level Simulation & Verification

Transmitter subblock
gate level synthesis
FFT64 synthesis result

Synthesis result report

Mapping to part: xcv1000ebg560-6
Global buffer usage summary: BUFGs +
BUFGPs: 1 of 4 (25%)
Mapping Summary: Total LUTs: 5448
(22%)
Mapper successful!
Process took 137.954 seconds realtime,
137.953 second cputime
WICHIP 38
Engineering
ideas

Gate Level Simulation & Verification

Transmitter subblock gate level simulation and

verification
Mapper, resimulated with netlist .vm file (output of
synthesis process, using Synplify Pro)
After debugging and retiming:
Library used: UNISIMS_VER, ROM and RAM modules

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Engineering
ideas

Hardware Emulation: Transmitter Top Block

Emulation Machine: Iprove (Dynalith) & 16-QAM Signal Space

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Emulation

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Engineering
ideas

Hardware Emulation: Receiver Top Block

Emulation Machine: Iprove (Dynalith) & 16-QAM Signal Space

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Engineering
ideas

Hardware Emulation: Transmitter Top Block

Emulation Machine: Aptix

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Engineering
ideas

Hardware Emulation: Receiver Top Block

Emulation Machine: Aptix

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Engineering
ideas

Hardware Emulation: Transmitter Top Block

Emulation Machine: Celaro & 16-QAM Signal Space

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Engineering
ideas

Hardware Emulation: Receiver Top Block

Area Report

Synplify & iPROVE : LUT 16586

Celaro : LUT 21432
Aptix : LUT 16493

Emulation Machine: Aptix & 16-QAM Singal Space

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Thanks and Cheers

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