Note: In order to modify/read the register contents of any peripheral, the clock to that
peripheral must be enabled by writing a 1 to the appropriate bit
Bit 7 ADC CLKEN. ADC module clock enable control bit
Bit 6 SCI CLKEN. SCI module clock enable control bit
Bit 5 SPI CLKEN. SPI module clock enable control bit
Bit 4 CAN CLKEN. CAN module clock enable control bit
Bit 3 EVB CLKEN. EVB module clock enable control bit
Bit 2 EVA CLKEN. EVA module clock enable control bit
For Bit 2 7:
0 Clock to module is disabled
1 Clock to module is enabled and running normally
Bit 0 ILLADR. Illegal Address detect bit
If illegal address occurs, this bit will be set.
Cleared by writing a 1 to it and should be cleared as part of the initialization
sequence.
Note: An illegal address will cause a Non-Maskable Interrupt (NMI).
System Control and Status Register 2
(SCSR2) Address 07019h