IMPROVEMENT OF SPICE
1. Is IR = 0
2. IR Id IC =0
3. Is = IR
4. IR = (V1 V2).G1
5. Id = Gd(eq).V2 +
Id(eq)
6. Ic = Gc(eq).V2 +
Ic(eq)
Resulting Matrix
Equation
Utilization Estimate:
Static Timing Analysis
Method of computing the expected
timing of a digital circuit without
requiring a simulation of the full
circuit
Floor Plan
Idea of SPICE on ZYNQ
CONCLUSION
We presented an empirical analysis for the SPICE
runtime and the type of matrices that typically arise in
circuit simulations. We studied the total SPICE
execution time and we demonstrated that the runtime
scales as the circuit size increases.
We presented a thorough analysis of the SPARSE 1.3 LU
solver package profiling every possible routine to
choose the best suitable candidate for hardware
acceleration. The internal matrix data structure of
SPARSE 1.3 was also discussed. We further presented
an empirical analysis of the runtime of various routines
within SPARSE 1.3, responsible solely for LU
factorization.
We gave a detail analysis of the hardware
design created and the major modifications
made on the existing SPARSE source code.
We also defined custom routines and data
types inside SPARSE 1.3 which support the
proper execution of our hardware design.
Finally we presented our implemented design
using HLS tools and reported its STA. Device
implementation was also reported in the form
of floor plane as generated by Vivado.
THANK YOU