systems
Jungmin Park
Project background
Parallel architecture
Parallel process High throughput
The worst case in hardware efficiency
Project objective
Design of High-performance and variable-length FFT processor for OFDM
systems
Project contents
Hardware efficiency and Shared memory architecture
area Proposed twiddle factor generator
Memory
8 banks
Dual port
Radix-8/4/2 BU
Memory address
generator and
Commutator
Twiddle factor
generator
Control unit
Operation of the proposed FFT processer (64-point data flow)
The Pipelined radix-8/4/2 DIF butterfly unit
S0 S1 Mode
0 0 4 parallel Radix-2
0 1 2 Parallel Radix-4
1 0 Radix-8 without multiplication
1 1 Radix-8 with multiplication
Application of proposed butterfly unit
64 2 Radix-8 Radix-8
VHDL modeling
How to verify and measure SQNR
SQNR 10 log10 (
(Re( A)) (Im( A))
2 2
)
(Re( A) Re( B)) (Im( A) Im( B))
2 2
FPGA synthesis
Xilinx ISE 12.4
Xilinx Virtex-5