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Lecture 7

8086 Interrupts
(& Macros)

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In this lecture

8086 Interrupts
8086 Assembly Wrap-up
Macros

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Interrupt

Breaks the normal sequence of execution of


instructions and diverts CPU execution to some
other program called Interrupt Service Routine
(ISR)

At the end of each instruction cycle, 8086


checks to see if any interrupts have been
requested

If interrupt is requested, the processor branches


to the ISR, executes the routine and transfers
control back to the main program
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8086 Interrupt Types

Two types of interrupts in 8086:

Hardware (External) interrupts


Non-Maskable interrupt (NMI)
o Edge triggered on a LOW to HIGH transition on pin NMI of 8086
Maskable interrupt (INTR)
o High level-triggered on pin INTR of 8086
o Can be masked by resetting IF (Interrupt flag)
(if IF is zero this interrupt is disabled)

Software (Internal) interrupts


Divide by zero, overflow
Interrupts initiated by INT instruction
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8086 Interrupt Types cntd

All interrupts (external or internal) can be


initiated by the INT instruction

INT instruction takes an 8 bit operand (type),


therefore 8086 supports up to 256 different
interrupt types
e.g. INT 0 is equivalent to divide by zero
interrupt
INT 2 is equivalent to NMI

Memory locations 00000H to 003FFH are


reserved for interrupt operations
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8086 Interrupt Typescntd
3FF TYPE 255
H INTERRUPT
3FC (Available)
H . Four bytes are reserved
. for each type of interrupt
. These bytes specify the
10H TYPE 3 address of the ISR for the
INTERRUPT
(Break Point)
interrupt (2 bytes for
0CH TYPE 2 segment address & 2
INTERRUPT
(NMI)1 bytes for offset address)
08H TYPE
INTERRUPT
04H (Single-step)
TYPE 0
INTERRUPT
00H (Divide by zero)
8086 Interrupt Vector
Table
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Interrupt Cycle

The following sequence of actions take place when


CPU acknowledges an interrupt

Flag register is pushed into stack


The IF flag is cleared (to disable INTR interrupt)
The TF (Trap Flag) is cleared (to disable Single-Step
interrupt)
CS register is pushed into stack
IP register is incremented by 2 and pushed into stack
Address of ISR is loaded to CS and IP

An IRET instruction at the end of the ISR returns


execution to the main program
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Interrupt Cyclecntd

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Interupt Priority

What happens if two or more interrupts occur at


the same time?

The highest-priority interrupt is serviced first then the


next highest priority interrupt is serviced and so on

Interrupt Priority
Divide by zero, INT Highest
n, INTO
NMI
INTR
Single-step Lowest

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Interrupt Example
INT 21h can be used for I/O operations in MS-DOS
systems

e.g. 1 The following instructions can be used to read a


character from keyboard
MOV ah, 01
INT 21h ; wait for character input from keyboard

e.g. 2 The following instructions can be used to display a


string on a monitor
LEA dx, str1 ; load starting add. of str1 on dx
MOV ah, 09
INT 21h

str1 db This is a string.$ ; define string


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8086 Assembly - Macros
A macro is a short hand for a sequence of other
statements (Instructions, directives, even other macros)
Syntax:
Name MACRO [variable(s)]
assembly statements
ENDM

e.g. A macro to convert ASCII to integer


atoi MACRO number
MOV al, number
AND al, 0Fh
MOV number, al
ENDM
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8086 Assembly - Macroscntd
atoi macro num
mov al,num
e.g. and al,0fh
mov num,al org 100h
endm
lea dx,str1
org 100h mov ah,9
int 21h
lea dx,str1 mov ah,1
mov ah,9 int 21h
int 21h mov bl,al
mov ah,1 mov al,bl
int 21h and al,0fh
mov bl,al mov bl,al
atoi bl ret
str1 db "enter number:
ret $"
str1 db "enter number:
$"
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More Readings

1. Dr. Manojs Handouts, Chapter 2


2. 8086 datasheet
3. emu8086 documentation

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