FPGA to ASIC ,

ASIC to ASIC ,
DSP to ASIC
CONVERSIONs
 Reduce Production Cost
Reduce your FPGA chip cost by more than 50%
from your product, with no effort from your side"


KaiSemi provides you a Guaranteed ASIC drop-in

replacement with No NRE payment, as Fast as 6-
14 weeks.


KaiSemi is the only vendor who owns in-house

semi-automated tools converting FPGA-to-ASIC
directly from netlist, any size of FPGA.


KaiSemi will convert your FPGA, covering the

whole ASIC workflow from customer decision
until 2nd source product shipping, seamless to
customer work.

About KaiSemi
 KaiSemi is a fablesssemiconductor vendor
specialized in product conversions of:
 FPGA-to-ASIC
 ASIC-to-ASIC
 DSP-to-ASIC
 MultiChip-to-ASIC
 www.kaisemi.com

 KaiSemi is a part of the Kai-Tek Group of
companies, a well established
representative, distributor and a R&D
service provider in the semiconductor
market with a strong financial backing.
 www.kai-tek.com


 The Kai-Tek Group is a member of the ATeG

“Advanced Technology Group”, a provider
of very strong technical offerings to its
customers, worldwide, from design-in to
KaiSemi services
Specialists of Cost-reduction chips


 Cost-reduction by FPGA-to-ASIC replacement.

 Any size of FPGA
 Seamless automated conversion directly from Netlist
 End-Of-Life continuation ASIC-to-ASIC replacement.
 Cost-reduction by merging multiple FPGAs/ASICs:
 into a single-die replacement, or
 into a multi-die single package replacement
 Drop-in replacement:
 fully compatible pin-to-pin 2nd source
 functional replacement with decreased package
 Cost-reduction and performance boost by DSP-to-ASIC.
Technical background:
Why replace FPGA by ASIC ?
Significant Cost reduction .
Significant Power saving.
Protection and copy-securing of Intellectual
Property.
Board cost reduction: No need for
Flash/EPROM chip; May reduce size in a multi-
FPGA case.
Eliminates power-up reconfiguration time.
Significant lower radiated EMI.
KaiSemi exclusive Workflow
KaiSemi flow Traditional flow

FPGA FPGA
Netlist RTL
 KaiSemi is focused on
converting, FPGA or ASIC, RTL fit to ASIC
directly from the FPGA’s Post-

in-house tools
P&R-Compiled Netlist. Functional
Simulation


KaiSemi
Full ASIC
Synthesis
 Kai-Semi has an exclusive set of
tools and processes to convert Timing +
Functional
directly from FPGA netlist to Simulation
ASIC final chip.
 ASIC Netlist

Converting from FPGA netlist DFT insertions

stage allows us to give Layout P&R
quality guarantee with no
functional risk and very fast Timing + Functional
cycle time. Simulation

FAB hand-off
KaiSemi business model
1.Functionality Guaranteed  “No good, no pay”.
2.Zero NRE Payment “Minimum Risk”.
3.Fastest cycle-time  “as fast as 6 - 14 weeks”.
4.Minimum customer intervention  “Fire and
forget”.
5.Any size FPGA “Minimum complexity limitation”.
1

5 2
Customer

4 3
 KaiSemi exclusive benefits
1. Functionality Guaranteed (No Good No Pay!), because:
 No RTL touch ! Functional source code is untouched.
 Using ONLY the Netlist outcome of the proven working FPGA.
 Proven in-house semi-automated developed conversion tool with experience
limits human errors
2. No NRE Payment (No Risk), because:
 Our business model is targeted to ease on the customer. Based on minimum
quantity ordering.
3. Fastest cycle-time, because:
 Shortening ASIC flow cycle by using automated process and by starting, higher,
from netlist stage
 Limiting the need for customers cycles of RTL flow, synthesis, verifications and
back-annotations.
 Having well established coherent work flow with FABs.

4. Minimum customer intervention (Fire & Forget), because:

 Customer is required to provide 2 main receivables:
1. The FPGA netlist
2. A verification test vectors.
 From that point on we proceed in posted mode, performing the whole ASIC
process until providing a final working chip.
KaiSemi Team

The KaiSemi team is built from experts, having 12

to 19 years of experience in the relevant
activity of FPGAs & ASIC conversions including
the full flow required for ASIC productization.
The team members have an experience of over
500 successful FPGAs & ASIC conversions.
 KaiSemi Additional Expertise
 Delivering a fully compatible pin-to-pin packaged device based on the existing
FPGA.


 Capability to fit compatible IPs, PLLs & I/Os of FPGAs to ASICs.



 Capability to provide various types of special cells like PLLs, DLLs, ADPLLs,
Multipliers, Power-On-Reset and broad range of IPs.


 KaiSemi has a well established  infrastructure with FABs and Processes in a

wide range of technology processes (0.5u, 0.35u, 0.18u, 0.13u, 0.09u). FAB-
Process is carefully defined based on the required frequency and other
design constraints, targeting to lower the cost.


 Supporting Commercial, Industrial and Military grades.



 Supporting Mixed signal and custom Analog cells solutions.



 Providing Custom low power design for specific modules.



 Supporting High performance libraries and clocking, convering both high speed
ASIC to ASIC
KaiSemi provides EOL (End Of Life) replacements for
ASICs taking care of the entire production process,
without customer involvement.


We guarantee a fully compatible drop-in replacement

for use as a reliable replacement part second source.


We do not charge NRE, we only get paid for the

working parts, so no risk is involved for the customer.


KaiSemi has also the capability to provide ASIC to ASIC

conversion for improving performance and/or using
improved replaceable ASIC libraries and IPs.
Multi Chip Merge
 Kaisemi provides advanced multi chip
solutions, that convert several
FPGA's into one ASIC, thus reducing
the total system cost and power
consumption immensely.


 We could also package your EOL (End

Of Life) ASIC or converted FPGA
along with its external memories
etc. thus enabling further cost
reduction and a reduced PCB
footprint.


 We have the ability to assemble

Multiple dies in a single package.

 DSP to ASIC Performance comparing example:
JPEG Encoder Case Study
Link: www.gmvhdl.com/fpga_for_dsp.html
Perf Platform
 KaiSemi offers a migration flow blcks/sec
6,835 TI C5410 160MHz
from DSP designs to a dedicated 12,602 Blackfin 300MHz
ASIC. 31,505
41,025
Blackfin 750MHz
FPGA + Impulse C 50MHz
 205,125 *KaiSemi ASIC1 250Mhz 0.13um
369,225 *KaiSemi ASIC2 450Mhz 0.09um
 This allows our customers to boost
DSP performance up to x100
from the existing top of the line * Estimated performance based ASIC frequency speedup
expensive DSP chips.

Performance per Cost comparing
 KaiSemi offers a development Link: www.latticesemi.com/lit/docs/generalinfo/e

environment flow and service to Cost MMAC/s Num of Device

import DSP designs into ASIC MMAC/s
¢6.4
¢3.3
¢0.8
¢0.024
¢0.027
4,000
1,200
7,000
119,000
214,200
Multipliers
4
28
476
476
TI DSP 300MHz
ECP-DSP20
250MHz
1GHz
*KaiSemi ASIC1
*KaiSemi ASIC2
while using evaluation 450MHz

verification on an FPGA.


 DSP design houses can now boost

performance per cost in their
applications, by moving from a
traditional DSP chip to a * Estimated performance/cost based ASIC area parallelism
Contacts
 Website:
 www.kaisemi.com


 Sales:
 sales@kaisemi.com
 Tel: +972-9-8920400
 Cell: +972-54-6675544


 Tech Support:
 support@kaisemi.com
 Tel: +972-9-8920400
 Cell: +972-54-4584445

Thank You