Digital VLSI Design

Lecture 2
Book: Sung Mo - Kang
Lecture 2
MOS System under External Bias
Lets check the behavior of MOS transistor under
externally applied bias voltages. Assume that the
substrate voltage, VB=0 and VG will be the
controlling parameter.
Depending on polarity and magnitude of VG,
there are three different operating regions for
MOS system:
Accumulation
Depletion
Inversion
Lecture 2
MOS System under External Bias
Accumulation:
If we apply negative voltage VG to gate electrode,
the holes in p-type substrate are attracted to the
semiconductor-dioxide interface.
Majority carrier concentration near the surface
becomes larger than equilibrium hole
concentration in substrate. So, this condition is
called Accumulation.
Lecture 2
MOS System under External Bias
Accumulation:
Lecture 2
MOS System under External Bias
Accumulation:
Because of negative surface potential
1. Electric field of semiconductor dioxide is directed
towards the electrode
2. Energy bands to upward near to surface.
So, at surface no. of holes increases, so electron
concentration decreases. Electrons will be
pushed into substrate.
Lecture 2
MOS System under External Bias
Depletion:
Now if we apply small positive voltage bias VG .
Since substrate bias is zero, oxide electric field
directed towards surface in this case.
The positive surface potential causes, the energy
bands to bend downwards near the surface. The
majority carriers will be repelled back into
substrate as a result of positive gate bias, and
these holes will leave negative charged fixed
acceptor ions behind.
Lecture 2
MOS System under External Bias
Depletion:
So, depletion region is created near surface.
Lecture 2
MOS System under External Bias
Depletion:
Size of depletion region xd can be found as a
function of surface potential s .
Assume that hole charge in a thin horizontal layer
parallel to surface is ,

The charge in surface potential is required to

displace this charge sheet dQ by distance Xd way
from surface can be found by Poissons Equation.
Lecture 2
MOS System under External Bias
Depletion:
Taking Integration vertically:
Lecture 2
MOS System under External Bias
Depletion:
So depth of depletion region is found by:

Charge of depletion region can be given as

Lecture 2
MOS System under External Bias
Inversion:
Further if we increase, Gate supply positively then
as a result of increasing surface potential, the
downward bending of the energy bands will
increase as well.
Eventually as mid gap Fermi level Ei becomes
smaller than Fermi level EFP on the surface, which
means that the substrate semiconductor becomes
n-type within this layer, electron density is larger
than hole density.
Lecture 2
MOS System under External Bias
Inversion:
Lecture 2
MOS System under External Bias
Inversion:
As n-type region created near surface by positive
gate supply is called inversion layer and this
condition is called surface inversion.
As per practical definition a surface is said to be
inverted when the density of mobile electron at
surface becomes equal to density of holes in the
bulk substrate.
Lecture 2
MOS System under External Bias
Inversion:
So, as surface is inverted any increase in gate
voltage will lead to increase mobile electron
concentration on surface but not to increase
deletion depth.
So, this depletion length at inversion is called xdm.
Lecture 2
MOS System under External Bias
Inversion:
At inversion, s = - F. So,
Lecture 2
Structure and Operation of MOS Transistor
MOSFET:
Lecture 2
Structure and Operation of MOS Transistor
MOSFET of n-channel is shown in figure. It is a
four terminal device with p-type substrate, in
which there are two n+ diffusion regions , the
drain and source are formed.
Surface of substrate region between drain and
source is covered with oxide region and a
metal electrode is deposited on the top of
Gate dielectric.
Lecture 2
Structure and Operation of MOS Transistor
Mid section of the device looks like MOS
structure . As the device is similar, n+ regions
can be used as source and drain as per the
polarity of applied terminal voltages and
direction of current.
When we apply gate voltage, conducting
channel will be formed between the two
diffusion region.
Lecture 2
Structure and Operation of MOS Transistor
Distance between these two diffusion regions
is called as channel length, lateral extent of
channel is called as channel width.
When gate bias is zero, MOS transistor does
not have any conducting channel, so it is
called enhancement type or enhancement
mode MOSFET.
If conducting channel already exists it is called
depletion type or depletion mode MOSFET.
Lecture 2
Structure and Operation of MOS Transistor
When we have p type substrate and n+ type
source and drain regions, the channel formed
is of n-type near surface, so it is called
n-channel MOSFET.
On the other hand for n-type substrate and p+
type diffusion regions, channel formed is of p
type near surface, so it is called p-channel
MOSFET.
Lecture 2
Structure and Operation of MOS Transistor
Symbols:
Lecture 2
Structure and Operation of MOS Transistor
Case: 1
Lecture 2
Structure and Operation of MOS Transistor
Case: 1
We keep source, drain and base terminal to
ground, and small voltage is applied to Gate
terminal in order to create conducting channel.
Under this bias condition, channel region behave
same as MOS structure. As we apply small voltgae
holes are repelled back into the substrate and the
surface of p type is depleted.
Since surface does not have any mobile carriers no
current will flow.
Lecture 2
Structure and Operation of MOS Transistor
Case: 2