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STANDARD VHDL EXAMPLES

BASIC LOGIC GATES


COMBINATIONAL LOGIC DESIGN
TYPICAL COMBINATIONAL
COMPONENTS
LATCH AND FLIP-FLOPS
TYPICAL SEQUENTIAL COMPONENTS
SEQUENTIAL LOGIC DESIGN

Introduction to VHDL
OR gate
library ieee;
use ieee.std_logic_1164.all;
entity OR_AATRI is
port( x: in std_logic; y: in std_logic;
F: out std_logic );
end OR_AARTI;
-- two descriptions provided
architecture OR_arch of OR_AARTI is architecture AARTI of OR_AARTI is
begin begin
process(x, y) F <= x or y;
begin -- compare to truth table end AARTI;
if ((x='0') and (y='0')) then F <= '0';
else F <= '1';
end if;
end process;
end OR_arch;
Introduction to VHDL
AND gate
library ieee;
use ieee.std_logic_1164.all;
entity AND_ent is
port( x: in std_logic; y: in std_logic;
F: out std_logic );
end AND_ent;
-- two descriptions provided
architecture behav1 of AND_ent is architecture behav2 of AND_ent is
begin begin
process(x, y) F <= x and y;
begin -- compare to truth table end behav2;
if ((x='1') and (y='1')) then F <= '1';
else F <= '0';
end if;
end process;
Introduction
end behav1; to VHDL
XOR gate
library ieee;
use ieee.std_logic_1164.all;

entity XOR_ent is
port( x: in std_logic; y: in std_logic; F: out std_logic );
end XOR_ent;
-- two descriptions provided
architecture behv1 of XOR_ent is architecture behv2 of XOR_ent is
begin begin
process(x, y) F <= x xor y;
begin -- compare to truth table end behv2;
if (x=y) then F <= 0';
else F <= 1';
end if;
end process;
end behv1;to VHDL
Introduction
NOR gate
library ieee;
use ieee.std_logic_1164.all;

entity NOR_ent is
port( x: in std_logic; y: in std_logic; F: out std_logic );
end NOR_ent;
-- two descriptions provided
architecture behv1 of NOR_ent is architecture behv2 of NOR_ent is
begin begin
process(x, y) F <= x nor y;
begin -- compare to truth table end behv2;
if (x='0' and y='0') then F <= '1';
else F <= '0';
end if;
end process;
end behv1;to VHDL
Introduction
NAND gate
library ieee;
use ieee.std_logic_1164.all;

entity NAND_ent is
port( x: in std_logic; y: in std_logic; F: out std_logic );
end NAND_ent;
-- two descriptions provided
architecture behv1 of NAND_ent is architecture behv2 of NAND_ent is
begin begin
process(x, y) F <= x nand y;
begin -- compare to truth table end behv2;
if (x='1' and y='1') then F <= '0';
else F <= '1';
end if;
end process;
end behv1;to VHDL
Introduction
XNOR gate
library ieee;
use ieee.std_logic_1164.all;

entity XNOR_ent is
port( x: in std_logic; y: in std_logic; F: out std_logic );
end XNOR_ent;
-- two descriptions provided
architecture behv1 of XNOR_ent is architecture behv2 of XNOR_ent is
begin begin
process(x, y) F <= x xnor y;
begin -- compare to truth table end behv2;
if (x/=y) then F <= '0';
else F <= '1';
end if;
end process;
end behv1;to VHDL
Introduction
COMBINATIONAL
LOGIC DESIGN

Introduction to VHDL
A simple example of VHDL Structure Modeling
-- we might define two components in two separate files, -- in main file, we use
port map statement to instantiate -- the mapping relationship between each
components -- and the entire circuit.
library ieee; -- top level circuit
library ieee; -- component #1
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use work.all;
entity OR_GATE is
entity comb_ckt is
port( X: in std_logic; Y: in std_logic; F2: out std_logic );
port( input1: in std_logic; input2: in std_logic;
end OR_GATE;
input3: in std_logic; output: out std_logic );
architecture behv of OR_GATE is
end comb_ckt;
begin process(X,Y)
architecture struct of comb_ckt is
begin
component AND_GATE is -- as entity of
F2 <= X or Y; -- behavior des.
AND_GATE
end process;
port( A: in std_logic; B: in std_logic; F1: out
end behv;
std_logic ); end component;
-------------------------------------------------------------
component OR_GATE is -- as entity of
library ieee; -- component #2
OR_GATE
use ieee.std_logic_1164.all;
port( X: in std_logic; Y: in std_logic; F2: out
entity AND_GATE is
std_logic ); end component;
port( A: in std_logic; B: in std_logic; F1: out std_logic );
signal wire: std_logic; -- signal just like wire
end AND_GATE;
begin -- use sign "=>" to clarify the pin mapping
architecture behv of AND_GATE is
Gate1: AND_GATE port map (A=>input1,
begin process(A,B)
B=>input2, F1=>wire);
begin F1 <= A and B; -- behavior des.
Gate2: OR_GATE port map (X=>wire,
end process;
Y=>input3, F2=>output);
end behv; to VHDL
Introduction end struct;
Test Bench for comb_ckt.vhd
Testbench is used to ensure design is working properly according to the specification.
-- assert statements are used to test the wrong value against our desired one. we should
test as many cases as possible, particularly, we should include upper and lower limits
library IEEE; use IEEE.std_logic_1164.all; -- Test case 2
use IEEE.std_logic_arith.all; T_input1 <= '1'; T_input2 <= '1'; T_input3 <= '1';
entity CKT_TB is -- empty entity wait for 10 ns;
end CKT_TB; assert (T_output=((T_input1 or T_input2) and
architecture TB of CKT_TB is -- declare the whole circuit T_input3))
(entity of comb_ckt.vhd) as a component. report "Failed Case1!" severity error;
component comb_ckt is port( input1: in std_logic; if (T_output/=((T_input1 or T_input2) and
input2: in std_logic; input3: in std_logic; T_input3)) then err_cnt := err_cnt +1; end if;
output: out std_logic ); -- Test case 3
end component; T_input1 <= '1'; T_input2 <= '0'; T_input3 <= '1';
signal T_input1, T_input2, T_input3, T_output: std_logic;
wait for 10 ns;
assert (T_output=((T_input1 or T_input2) and
begin
T_input3)) report "Failed Case1!" severity error;
U_UT: comb_ckt port map
if (T_output/=((T_input1 or T_input2) and
(T_input1,T_input2,T_input3,T_output);
T_input3)) then err_cnt := err_cnt +1; end if;
process
-- Test case 4
variable err_cnt: integer := 0;
T_input1 <= '0'; T_input2 <= '1'; T_input3 <= '0';
begin -- Test case 1
wait for 10 ns;
T_input1 <= '0'; T_input2 <= '0'; T_input3 <= '0'; wait for
assert (T_output=((T_input1 or T_input2) and
10 ns;
T_input3)) report "Failed Case1!" severity error;
assert (T_output=((T_input1 or T_input2) and T_input3))
if (T_output/=((T_input1 or T_input2) and
report "Failed Case1!" severity error;
T_input3)) then err_cnt := err_cnt +1; end if;
ifIntroduction
(T_output/=((T_input1
to VHDL or T_input2) and T_input3))
summary of all the tests to see if any errors

-------------------------------------------------------------------
if (err_cnt=0) then
assert false report "Testbench completed successfully!" severity note;
else assert true report "Something wrong, try again pls!"
severity error;
end if; wait; -- stop running
end process;
end TB;
-------------------------------------------------------------------
configuration CFG_TB of CKT_TB is
for TB
end for;
end CFG_TB;
--------------------------------------------------------------------

Introduction to VHDL
VHDL model for tri state driver
this driver often used to control system outputs

library ieee;
use ieee.std_logic_1164.all;

entity tristate_dr is
port( d_in: in std_logic_vector(7 downto 0); en: in std_logic;
d_out: out std_logic_vector(7 downto 0) );
end tristate_dr;

architecture behavior of tristate_dr is


begin process(d_in, en)
begin
if en='1' then d_out <= d_in;
else -- array can be created simply by using vector
d_out <= "ZZZZZZZZ";
end if;
end process;
end behavior;

Introduction to VHDL
summary of all the tests to see if any errors

-------------------------------------------------------------------
if (err_cnt=0) then
assert false report "Testbench completed successfully!" severity note;
else assert true report "Something wrong, try again pls!"
severity error;
end if; wait; -- stop running
end process;
end TB;
-------------------------------------------------------------------
configuration CFG_TB of CKT_TB is
for TB
end for;
end CFG_TB;
--------------------------------------------------------------------

Introduction to VHDL
Signal vs. Variable
Siganls are used to connect the design components and must carry the
information between current statements of the design. On the other
hand, variables are used within process to compute certain values.
The following example shows their difference:
library ieee;
use ieee.std_logic_1164.all;
entity sig_var is
port( d1, d2, d3: in std_logic;
res1, res2: out std_logic);
end sig_var;

architecture behv of sig_var is


signal sig_s1: std_logic;

begin
proc1: process(d1,d2,d3) proc2: process(d1,d2,d3)
variable var_s1: std_logic; begin
begin sig_s1 <= d1 and d2;
var_s1 := d1 and d2; res2 <= sig_s1 xor d3;
res1 <= var_s1 xor d3; end process;
end process;
Introduction to VHDL end behv;
TYPICAL
COMBINATIONAL
COMPONENTS

Introduction to VHDL
COMBINATIONAL COMPONENTS

The following behavior style codes demonstrate the concurrent and


sequential capabilities of VHDL.

The concurrent statements are written within the body of an


architecture. They include concurrent signal assignment, concurrent
process and component instantiations (port map statement).

Sequential statements are written within a process statement, function


or procedure. Sequential statement include case statement, if-then-
else statement and loop statement.
VHDL code for 4:1 multiplexor
library ieee;
use ieee.std_logic_1164.all;
entity Mux is
port( I3: in std_logic_vector(2 downto 0); I2: in std_logic_vector(2 downto 0);
I1: in std_logic_vector(2 downto 0); I0: in std_logic_vector(2 downto 0);
S: in std_logic_vector(1 downto 0); O: out std_logic_vector(2 downto 0) );
end Mux;

architecture behv1 of Mux is architecture behv2 of Mux is


begin begin -- use when.. else statement
process(I3,I2,I1,I0,S) O <= I0 when S="00"
begin -- use case statement else I1 when S="01"
case S is else I2 when S="10"
when "00" => O <= I0; else I3 when S="11"
when "01" => O <= I1; else "ZZZ";
when "10" => O <= I2; end behv2;
when "11" => O <= I3;
when others => O <= "ZZZ";
end case;
end process;
end behv1;

Introduction to VHDL
2:4 Decoder
library ieee;
use ieee.std_logic_1164.all;
entity DECODER is
port( I: in std_logic_vector(1 downto 0);
O: out std_logic_vector(3 downto 0) );
end DECODER;

architecture behv of DECODER is


begin -- process statement architecture when_else of DECODER is
process (I) begin -- use case statement begin -- use when..else statement
case I is when "00" => O <= "0001"; O <= "0001" when I = "00" else
when "01" => O <= "0010"; "0010 when I = "01" else
when "10" => O <= "0100"; "0100" when I = "10" else
when "11" => O <= "1000"; "1000" when I = "11" else
when others => O <= "XXXX"; "XXXX";
end case; end when_else;
end process;
end behv;

Introduction to VHDL
n-bit adder
-- function of adder: -- A plus B to get n-bit sum and 1 bit carry
-- we may use generic statement to set the parameter -- n of the adder.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ADDER is
generic(n: natural :=2);
port( A: in std_logic_vector(n-1 downto 0);
B: in std_logic_vector(n-1 downto 0);
carry: out std_logic;
sum: out std_logic_vector(n-1 downto 0) );
end ADDER;

architecture behv of ADDER is -- define a temparary signal to store the result


signal result: std_logic_vector(n downto 0);
begin
-- the 3rd bit should be carry
result <= ('0' & A)+('0' & B);
sum <= result(n-1 downto 0);
carry <= result(n);
end behv; to VHDL
Introduction
n-bit Comparator
this simple comparator has two n-bit inputs & -- three 1-bit outputs
library ieee;
use ieee.std_logic_1164.all;

entity Comparator is
generic(n: natural :=2);
port( A: in std_logic_vector(n-1 downto 0); B: in std_logic_vector(n-1 downto 0);
less: out std_logic; equal: out std_logic; greater: out std_logic );
end Comparator;

architecture behv of Comparator is


begin
process(A,B)
begin
if (A<B) then less <= '1';
equal <= '0';
greater <= '0';
elsif (A=B) then less <= '0';
equal <= '1';
greater <= '0';
else less <= '0'; equal <= '0';
greater <= '1';
end if;
end process; toend
Introduction behv;
VHDL
ALU
-- ALU stands for arithmatic logic unit. -- It perform multiple operations
according to -- the control bits. -- we use 2's complement subraction in
this example -- two 2-bit inputs & carry-bit ignored
library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity ALU is port( A: in std_logic_vector(1 downto 0); B: in std_logic_vector(1 downto 0);


Sel: in std_logic_vector(1 downto 0); Res: out std_logic_vector(1 downto 0) );
end ALU;

architecture behv of ALU is


begin
process(A,B,Sel)
begin -- use case statement to achieve -- different operations of ALU
case Sel is when "00" => Res <= A + B;
when "01" => Res <= A + (not B) + 1;
when "10" => Res <= A and B;
when "11" => Res <= A or B;
when others => Res <= "XX";
end case;
end process;
end behv; to VHDL
Introduction
MULTIPLIER
Example of doing multiplication showing (1) how to use variable with in process (2)
how to use for loop statement (3) algorithm of multiplication
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all; -- two 4-bit inputs and one 8-bit outputs

entity multiplier is
port( num1, num2: in std_logic_vector(1 downto 0); product: out std_logic_vector(3 downto 0) );
end multiplier;

architecture behv of multiplier is


begin process(num1, num2)
variable num1_reg: std_logic_vector(2 downto 0); variable product_reg: std_logic_vector(5 downto 0);
begin
num1_reg := '0' & num1;
product_reg := "0000" & num2; -- use variables doing computation -- algorithm is to repeat shifting/adding
for i in 1 to 3 loop
if product_reg(0)='1' then product_reg(5 downto 3) := product_reg(5 downto 3) + num1_reg(2 downto 0); end
if;
product_reg(5 downto 0) := '0' & product_reg(5 downto 1);
end loop; -- assign the result of computation back to output signal
product <= product_reg(3 downto 0);
end process;
Introduction to VHDL
end behv;
LATCHES
&
FLIP FLOPS

Introduction to VHDL
Simple D Latch
latch is simply controlled by enable bit -- but has nothing to do with clock sigal --
notice this difference from flip-flops
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all; -- Simple D Latch

entity D_latch is
port( data_in: in std_logic; enable: in std_logic; data_out: out std_logic );
end D_latch;

architecture behv of D_latch is


begin -- compare this to D flipflop
process(data_in, enable)
begin
if (enable='1') then -- no clock signal here
data_out <= data_in;
end if;
end process;
end behv;

Introduction to VHDL
D Flip-Flop
Flip-flop is the basic component in sequential logic design.
we assign input signal to the output at the clock rising edge
library ieee ;
use ieee.std_logic_1164.all;
use work.all;

entity dff is
port( data_in: in std_logic; clock: in std_logic; data_out: out std_logic );
end dff;

architecture behv of dff is


begin process(data_in, clock)
begin -- clock rising edge
if (clock='1' and clock'event) then
data_out <= data_in;
end if;
end process;
end behv;

Introduction to VHDL
JK Flip-Flop
Flip-flop is the basic component in sequential logic design.
we assign input signal to the output at the clock rising edge
library ieee ;
use ieee.std_logic_1164.all;
use work.all;

entity JK_FF is
port ( clock: in std_logic; J, K: in std_logic; reset: in std_logic; Q, Qbar: out std_logic );
end JK_FF;

architecture behv of JK_FF is -- define the useful signals here


signal state: std_logic;
signal input: std_logic_vector(1 downto 0);
begin -- combine inputs into vector
input <= J & K; case (input) is when "11" => state <= not state;
p: process(clock, reset) is when "10" => state <= '1';
begin when "01" => state <= '0';
if (reset='1') when others => null;
then state <= '0'; end case;
elsif (rising_edge(clock)) end if;
then -- compare to the truth table end process; -- concurrent statements
Q <= state;
Qbar <= not state;
Introduction to VHDL
end behv;
VHDL for Simulation & Synthesis

Test Vector Executable Results,


Specification
= Errors
Generator

A Series of
Test
Refined
Vectors
Models
Final Chip
Model
VHDL for Simulation & Synthesis

VHDL requirements for Simulation


Creation of test benches =>
File I/O
Detection of errors (function & timing)
Multiple simultaneous models
Combination of low & high level models
(for efficiency)
VHDL for Simulation & Synthesis

VHDL requirements for HW Description


Behavioral models =>
Combinatorial & Sequential Logic
RTL models
Structural models
Timing models
VHDL for Simulation & Synthesis

Requirements for VHDL Synthesis Tools


Pre- & post synthesis behavior should be identical
Synthesis should be efficient =>
Requires interaction with place & route tools
Logic Synthesis
FSM Synthesis
Area & Timing Optimization
New possibilities

VHDL frees the designer from having to use von Neumann


structures
(Neumann Jnos = John von Neumann)
It allows him to work with real concurrency instead of
sequential machines
This opens up completely new possibilities for the designer
Reasons for using VHDL

Shorter development times for electronic design


Simpler maintenance
Traditional way: schematic design
Origin of the VHDL

VHDL originated in the early 1980s


The American Department of Defense initiated the development of
VHDL in the early 1980s
because the US military needed a standardized method of describing
electronic systems
VHDL was standardized in 1987 by the IEEE
It is now accepted as one of the most important standard
languages for
specifying
verifying
designing of electronics

Introduction to VHDL
Standardization 1
IEEE standard specification language (IEEE 1076-1993)
for describing digital hardware used by industry worldwide
VHDL enables hardware modeling from the gate level to
the system level

All the major tool manufacturers now support the VHDL


standard
VHDL is now a standardized language, with the advantage
that it is easy to move VHDL code between different
commercial platforms (tools)
=> VHDL code is interchangeable among the different tools
Standardization 2
VHDL is an acronym of VHSIC Hardware Description
Language
VHSIC is an acronym of Very High Speed Integrated
Circuits
All the major tool manufacturers now support the VHDL
standard
VHDL is now a standardized language, with the advantage
that it it easy to move VHDL code between different
commercial platforms (tools)
=> VHDL code is interchangeable among the different tools

Introduction to VHDL
Standardization 3
It was the American Department of Defense which initiated
the development of VHDL in the early 1980s because the US
military needed a standardized method of describing
electronic systems
VHDL was standardized in 1987 by the IEEE
IEEE Std-1076-1987
ANSI Standard in 1988
Added Support for RTL Design
VITAL: VHDL Initiative Towards ASIC Library
Revised version in 1993
IEEE Std-1076-1993

Introduction to VHDL
Standardization 4
1995:
numeric_std/bit: IEEE-1076.3
VITAL: IEEE-1076.4
1999: IEEE-1076.1 (VHDL-AMS )
2000:
IEEE-1076-2000
IEEE-1076.1-2000 (VITAL-2000, SDF 4.0)
Added mixed-signal support to VHDL in 2001 ->
VHDL-AMS
IEEE Std-1076.1-2001
2002: IEEE-1076-2002

Introduction to VHDL
Tools

Good VHDL tools, and VHDL simulators in particular,


have also been developed for PCs
Prices have fallen dramatically, enabling smaller
companies to use VHDL, too
There are also PC synthesis tools, primarily for FPGAs and
EPLDs
Usage

High-tech companies
Texas Instruments, Intel use VHDL
most European companies use VHDL
Universities
VHDL groups to support new users
IEEE
IEEE is the Institute of Electrical and Electronics
Engineers
The reference manual is called IEEE VHDL Language
Reference Manual Draft Standard version 1076/B
It was ratified in December 1987 as IEEE 1076-1987
Important:
the VHDL is standardized for system specification
but not for design
Technology independence
The design of VHDL components can be technology-independent
or more-or-less technology independent for a technical family
The components can be stored in a library for reuse in several
different designs
VHDL models of commercial IC standard components can now
be bought, which is a great advantage when it comes to verifying
entire circuit boards
Analog world
VHDL has not yet been standardized for analog electronics
Standardization is in progress on VHDL with an analog
extension (AHDL) to allow analog systems to be described
as well
This new standard will be based wholly on the VHDL
standard and will have a number of additions for describing
analog functions
VHDL-Related Newsgroups

comp.arch.fpga
comp.lang.vhdl
comp.cad.synthesis

Introduction to VHDL
Other HDL languages
There are several other language extensions built to either aid in RTL construction
or assist in modeling:
ParaCore - http://www.dilloneng.com/paracore.shtml
RubyHDL - http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtml
MyHDL - http://jandecaluwe.com/Tools/MyHDL/Overview.shtml
JHDL - http://www.jhdl.org/
Lava - http://www.xilinx.com/labs/lava/
HDLmaker - http://www.polybus.com/hdlmaker/users_guide/
SystemC
AHDL http://www.altera.com
It is good for Altera-made chips only, which limits its usefulness
But it is easy to pick up and use successfully
The main purpose of a language -- programming, hdl, or otherwise -- is to ease the
expression of design

Introduction to VHDL
Verilog
Verifying Logic
Phil Moorby from Gateway Design Automation in 1984 to 1987
Absorbed by Cadence
Cadence's ownership of Verilog => others support VHDL
Verilog-XL simulator from GDA in 1986
Synopsis Synthesis Tool in 1988
In 1990 became open language
OVI: Open Verilog International
IEEE Standard in 1995
IEEE Std-1364-1995
Last revision in 2001
IEEE Std-1364-2001
Ongoing work for adding
Mixed-signal constructs: Verilog-AMS
System-level constructs: SystemVerilog

Introduction to VHDL
VHDL vs. Verilog
VHDL Verilog
All abstraction levels All abstraction levels
Complex grammar Easy language
Describe a system (everything) Describe a digital system
Lots of data types Few data types
User-defined package & library No user-defined packages
Full design parameterization Simple parameterization
Easier to handle large designs
Very consistent language. Code written and Less consistent language. If you don't
simulated in one simulator will behave follow some adhoc methodology for coding
exactly the same in another simulator. E.g. styles, you will not get it right.
strong typing rules.

It executes differently on different platforms


unless you follow some adhoc coding rules.

Introduction to VHDL
VHDL vs. Verilog (Cont.)
It does seem that Verilog is easier for designing at the
gate-level, but that people who do higher level simulations express a
preference for VHDL
VHDL places constraints on evaluation order that limit the
optimizations that can be performed
Verilog allows the simulator greater freedom
For example, multiple levels of zero-delay gates can be collapsed into a single
super-gate evaluation in Verilog
VHDL requires preserving the original number of delta cycles of delay
in propagating through those levels

VHDL Verilog
In Europe the VHDL is the most popular
language
Based on Pascal language Based on C language
Most FPGA design in VHDL Most ASIC design in Verilog
Introduction to VHDL
VHDL vs. Verilog: Process block
VHDL:
process (siga, sigb)
begin
...
end;
Verilog:
always @ (siga or sigb)
begin
.
end

Introduction to VHDL
VHDL vs. Verilog:
Concurrent Signal Assignment

VHDL:
c <= a and b;
Verilog:
assign c = a & b ;

Introduction to VHDL
VHDL vs. Verilog: Signal Delays
VHDL:
a <= transport b after 1 ns;
Verilog:
#1 assign a = b;
a output is delayed by 1 time unit
The # operator is the delay operator
# N will delay for N simulation units
Delays can assigned to both inputs and outputs
#1 assign a = #1 b;
b is delayed by 1 unit, then assigned to a, which is then delayed by 1 time
unit

Introduction to VHDL
VHDL vs. Verilog: Clock Generator
VHDL:
signal clk : std_logic := 0;
process
begin
clk <= not (clk) after clkperiod/2;
wait on clk;
end;
Verilog:
initial clk = 0;
always #(clkperiod/2) clk = ~ clk;

Introduction to VHDL
Verilog Weakness
Not well suited for complex, high level modeling
No user defined type definition
No concept of libraries, packages, configurations
No generate statement - cant build parameterized structural models
No complex types above a two-dimensional array

Introduction to VHDL
VHDL vs. Verilog:
Managing Large designs

VHDL:
Configuration, generate, generic and package statements all help manage
large design structures
Verilog:
There are no statements in Verilog that help manage large designs

Introduction to VHDL
VHDL vs. Verilog:
Procedures and Tasks

VHDL:
allows concurrent procedure calls

Verilog:
does not allow concurrent task calls

Introduction to VHDL
VHDL vs. Verilog:
Structural Replication

VHDL:
The generate statement replicates a number of instances
of the same design-unit or some sub part of a design, and
connects it appropriately

Verilog:
There is no equivalent to the generate statement in
Verilog.

Introduction to VHDL
Languages under development
SystemVerilog
Extending Verilog to higher levels of abstraction for architectural and
algorithm design and advanced verification
VHDL 200x
Goal of VHDL Analysis and Standards Group (VASG):
Enhance/update VHDL for to improve performance, modeling capability,
ease of use, simulation control, and the type system
e.g.: Data types and abstractions:

variant records
interfaces

Introduction to VHDL