Digital Logic

Progammable
Standard Logic ASICs Full Custom
Logic Devices

Microprocessor
SPLDs CPLDs FPGAs & RAM

TTL CMOS Gate Standard

74xx 4xxx Arrays Cells

Acronyms
SPLD = Simple Prog. Logic Device
PAL = Prog. Array of Logic
CPLD = Complex PLD
FPGA = Field Prog. Gate Array
ASIC = Application Specific IC
 Programmable Logic Devices
FPLD (Field-Programmable Logic Device)
Supplied with no predetermined logic function
Programmed by user to implement any digital
logic function
Require specialized computer software for
design and programming.
Implementation of digital circuits with low cost
and low risk.
Technology of choice for low to medium volume
products (say hundreds to few 10s of thousands
per year).
Good and low cost design softwares.
 Programmable Logic Devices
SPLDs (Simple PLDs)
ROM, PLA or PAL
Small gate count, fixed internal routing, deterministic
propagation delays
CPLDs
Multiple SPLDs onto a single chip
Programmable interconnect
FPGAs
An array of logic blocks
Large number of gates, user selectable interconnection,
delays depending on design and routinig
A high ratio of flip-flops to logic resources
 Simple PLD Types
ROM (Read Only Memory)
Fixed AND plane
Programmable OR plane
PLA (Programmable Logic Array)
Programmable AND plane
Programmable OR plane
PAL (Programmable Array Logic)
Programmable AND plane
Fixed OR plane
 Programmablility
For all kinds of PLDs
One Time Programmable (OTP)
Re-Programmable (RP)
SPLD Structure
 ROM, PALs and PLAs
Pre-fabricated building block
x1 x 2 xn of many AND/OR gates (or NOR,
NAND)

"Personalized" by making or
Input buffers breaking connections among
and the gates
Inverters

x1 x1 xn xn
P1
P2
Output inverters
AND plane OR plane
Pk

f1 fm
 All possible connections are available
before programming

A B C

F0 F1 F2 F3
A B C

Unwanted connections are "blown"

AB

/BC

A /C

/B /C

F0 F1 F2 F3

Note: some array structures

work by making connections
rather than breaking them
 PLA Before
programming

A B C D

AB PLA After programming

AB
F0 = A B + A' B'
CD F1 = C D' + C' D
CD

F0 F1
 Difference between Programmable Array Logic (PAL) and
Programmable Logic Array (PLA):

PAL : AND array programmable

OR array fixed

A given column of the OR array has access to only a subset

of the possible product terms
Design Example: BCD to Gray
Code Converter
Truth Table

A B C D W X Y Z
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 1 1 1 0
0 1 1 0 1 0 1 0
0 1 1 1 1 0 1 1
1 0 0 0 1 0 0 1
1 0 0 1 1 0 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 0 X X X X
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X
 A A
AB AB
CD 00 01 11 10 CD 00 01 11 10

00 0 0 X 1 00 0 1 X 0

01 0 1 X 1 01 0 1 X 0
D D
11 0 1 X X 11 0 0 X X
C C
10 0 1 X X 10 0 0 X X

B B
K-ma p f or W K-ma p f or X

A A
AB AB
CD 00 01 11 10 CD 00 01 11 10

00 0 1 X 0 00 0 0 X 1

01 0 1 X 0 01 1 0 X 0
D D
11 1 1 X X 11 0 1 X X
C C
10 1 1 X X 10 1 0 X X

B B
K-ma p f or Y K-ma p f or Z

W=A+BD+BC
Minimized
X = B C'
Functions:
Y=B+C
Z = A'B'C'D + B C D + A D' + B' C D'
A B C D
A
BD
BC

0
BC
0
0
0
B
C
0
0
ABCD
BCD
AD
BCD

W X Y Z
 \A \A
A 1
\B
4
\C
B D
2 3 W
D
B
C 3
B 2 D
C 4 4 Z
A
5
B D 1
\D
22 1 X \B
C 1
C 3
\C \D

2 Y 1: 7404 hex inverters

B 1 2,5: 7400 quad 2-input NAND
\B 3: 7410 tri 3-input NAND
4: 7420 dual 4-input NAND

Code Converter Discrete Gate Implementation

4 SSI Packages vs. 1 PLA/PAL Package!
 Example: Magnitude Comparator
A B C D

ABCD

A A
ABCD
AB AB
CD 00 01 11 10 CD 00 01 11 10 ABCD
00 1 0 0 0 00 0 1 1 1
ABCD
01 0 1 0 0 01 1 0 1 1
D D
AC
11 0 0 1 0 11 1 1 0 1
C C
10 0 0 0 1 10 1 1 1 0 AC

B B BD
K-map for EQ K-map for NE
BD
A A
AB AB
ABD
CD 00 01 11 10 CD 00 01 11 10
00 0 0 0 0 00 0 1 1 1 BCD

01 1 0 0 0 01 0 0 1 1 ABC
D D
11 1 1 0 1 11 0 0 0 0
C C
BCD
10 1 1 0 0 10 0 0 1 0

B B
K-map for LT K-map for GT
Transistor-Level Structure
CPLD Structure
 CPLD Overview
Higher Capacity than SPLD
~ 5000 gates
Reasonable speed
Simple Systems
 Why CPLDs?
For larger applications, we could simply increase the
number of inputs and outputs in a conventional SPLD

e.g., 16V8 20V8 22V10
why not keep this trend going 32V16 128V64 ?
Problems:
n times the number of inputs and outputs requires n2 as
much chip area too costly
logic gets slower as number of inputs to AND array
increases
Solution:
multiple PLDs with a relatively small (fast) programmable
interconnect
less general than a single large PLD, but we can use
software to partition our design into smaller PLD blocks
 CPLD Structure
A Simple PLD (or SPLD) is
usually a PLA or a PAL
A Complex PLD (CPLD) is
an arrangement of multiple
SPLD-like blocks on a
single chip.
Alternative names include:
enhanced PLD (EPLD)
superPAL
megaPAL
 Who makes the CPLDs?

Manufacturer CPLD Products URL

Altera MAX 5000, 7000 & 9000 www.altera.com

Altmel ATF & ATV www.atmel.com
Cypress FLASH370, Ultra37000 www.cypress.com
Lattice ispLSI 1000 to 8000 www.latticesemi.com
Philips XPLA www.philips.com
Vantis MACH 1 to 5 www.vantis.com
Xilinx XC9500 www.xilinx.com
Field Programmable Gate Array
Two dimensional
structure
Programmable
Three elements:
Logic blocks
I/O blocks
Interconnection wires and switches
Field Programmable Gate Array
Interconnection
Switches
Logic
Block FPGAs
Three elements:
Logic blocks
I/O blocks
Interconnection wires
and switches

I/O
Block
CAD Design Flow
DESIGN CONCEPTION

DESIGN ENTRY
(Truth Table, Schematic capture, HDL)

INITIAL SYNTHESIS TOOLS

(Simple synthesis, Translation, Merge)

FUNTIONAL SIMULATION
No
Design correct?
Yes
Logic synthesis
Physical design
Timing simulation

Overview
Two Common Languages
of HDLs
Verilog
VHDL
Other
SystemC
Open source, C++ code for hardware modeling
CDL (Computer Design Language)
Simple academic language, data flow level, developed in
1965
ISPS (Instruction Set Processor Specification)
Single level of abstraction, Developed in 1971
AHPL (A Hardware Programming Language)
Data flow & structural levels, Unfamiliar syntax, Full support
by design tools, developed in 1970
ABEL (Data I/O Corporation, now Lattice Semiconductor)
AHDL (Altera Corp.)
CUPL (Logical Devices Inc.)
 VHDL
VHSIC HDL: Very High Speed Integrated Circuits
Hardware Description Language
DARPA workshop on VHSIC in 1981
DARPA release requirement in 1983
A language for hardware documentation
VHDL 7.2 in 1985
IEEE standard in 1987
ANSI standard in 1988
For RTL design VITAL added
VITAL(VHDL Initiative Towards ASIC Library)
IEEE revised VHDL & VITAL in 1993
Final review of standard in 2001
 PLA table

Equations Produc t Inputs Outputs

term A B C F0 F1 F2 F3
F0 = A + B' C' AB 1 1 - 0 1 1 0
F1 = A C' + A B Reus e
F2 = B' C' + A B BC - 01 0 0 0 1
F3 = B' C + A AC 1 - 0 0 1 0 0 of
terms
BC - 00 1 0 1 0
A 1 - - 1 0 0 1

Input Side: Output Side:

1 = asserted in term 1 = term connected to output

0 = negated in term 0 = no connection to output
- = does not participate
 PAL
Architecture
Recall the PAL
device we studied
earlier
PAL16L8
16 inputs
32 input AND gates
up to 8 output
functions
Outputs are
selectable between
OR/NOR
PAL 16 L 8
PAL 16R6
GAL 22V10

More inputs
More product
terms
More flexibility