Raimund Ubar
raiub@pld.ttu.ee
Lectures
Testability of Digital Systems
Design for Testability Methods
BIST/BISD
Practical Works
Two laboratory works
Course work
Tiina Ubar
7
Raimund Ubar Integreeritud elektroonikassteemide ja biomeditsiinitehnika tippkeskus
98 %
Microprocessor
market shares
9
Introduction: Testing World
Test
experiment
Test
System result
(BIST)
System Fault
Test model dictionary
Go/No go
Test generation
Located defect
Test tools
What is a test?
Test-
program How many
test patterns
are needed
12 + 10 = ? to test an adder?
Processor
Diagnosis
22
Test
results
11
Hierarchy: Divide and Conquer
Engineer vs. computer: The best place to start is
with a good title.
To generate a test Then build
for a component a song around it.
in a system, (Wisdom of country music)
the computer
needed
2 days and 2 nights Sea of gates
An engineer
did it by hand
with 15 minutes &
Sequence 16 bit
1
of 216 bits counter
So, why computers? System
13
Raimund Ubar
Defect
Expert systems
011001
were used in Europe
? Know-how but not in US
Defekt
Gordion
Knot
011001
Hard-to-test-
? part
New paradigm
ScanPath Design
011001 15
mindmappingsoftwareblog.com
Raimund Ubar
16
Jean-Simon Berthlemy (17431811)
Making Systems Transparent
IN OUT
Combinational
circuit
q R q
theisleofwightcomputergeek.co.uk
IN OUT
Combinational
circuit
Scan-IN
q R q
Scan-Path design strategy
Scan-OUT
System
under
test
Improving
Improving observability
controllability
Control points
Proof:
011 011 001
& 001 &
101 101
?
&
011 001
& 011
101 1
010 & 001
101
General
System Scan-Path FSM CC NAND
Solution?
IN OUT
Combinational
circuit
q R q
theisleofwightcomputergeek.co.uk
IN OUT
Combinational
circuit
Scan-IN
q R q
Scan-Path design strategy
Scan-OUT
Source: Intel
Source: Elcoteq
On circuit
Test pattern generation Test Pattern Generation (TPG)
Response verification
Random pattern Circuitry Under Test
BIST
generation, Control Unit
CUT
very long tests
Response compression Test Response Analysis (TRA)
IC
Tester
Memory
BIST BIST BIST
System on Chip
Design of a circuit
Evaluation of the testability of the circuit
Redesign for testability
Control points selection, optimization
Scan path, optimization
Built-in self-test. Design of solutions
Experimental research
In-circuit
Test pattern generation Test Pattern Generation (TPG)
Response verification
Pseudorandom test Circuitry Under Test
BIST
generation, Control Unit
CUT
very long tests
Hybrid test solutions Test Response Analysis (TRA)
IC
Response compression
4
1. Design of a combinational circuit
A B C x z for the following functionality
Vers. Vers
k1 k2 k3 k4 k5 k6 k1 k2 k3 k4 k5 k6
No. no.
1 1 1 1 0,1 0,2 0,5 8 1 1 1 1,5 0,1 0,5
Signature Analyzer
OP
1- controllability:
CP = 0 - normal working mode
Block 1 1 Block 2
CP = 1 - controlling Block 2
with signal 1
CP
Combinational circuit
Hard
to test
faults
Fault Coverage
Pseudorandom
Using many seeds: test:
0 2n-1
Time
Counter 2 Counter 1 CL
11. Compare the results in tasks 4, 5, 7, 8 and 10. Which solution is the best
and why? Draw the block-level final structure of the selected best BIST
solution.
12. Present a report of the course work.