Introduction
Problem Statement
Objectives and Scope
Literature Review
General Methodology
The Proposed Oscillator
High-Level Validation
Modeling in Verilog
Implementation on FPGA
Summary of Contributions
Conclusions and future workand Future Work
Introduction
The two main problems in DPLL as a synchronization system are the high
operation frequencies and the requirement of low phase noise performance.
A second challenge is how to employ the digital control method with the
Digital Controlled LC Oscillator (DCLCO) that is characterized by a high Q
performance.
Lee et al. 2013 accomplish low phase noise and low a bang-bang phase CRs: providing relaying service to PUs. Input / output frequency multiplication
power at the same time detector PUs: selecting best relaying services
Lin 2000 This design is aimed to achieve 210 Bidders (CRs) employs a DCO that comprises an LC Input / output frequency multiplication
ps peak to peak jitter oscillator with digital and tunable
varactor banks.
Salvatore et al. an ADPLL for wireless applications Input / output frequency multiplication
2009 in the WiMAX DLL based TDC DCO is consisting in the LC tank
with BBPD
Staszewski et al. a single-chip GSM/EDGE transceiver LC oscillator as the DCO Input / output frequency multiplication
2005
TDC
Helal et al. (2008) clock multiplier Input / output frequency multiplication
TDC (time to digital Ring Oscillator
converter)
Tierno et al. (2008) frequency synthesizer for RF wireless Input / output frequency multiplication
a BBPFD 3-stages static inverter based ring
oscillator
General Methodology
The Proposed Oscillator
Injection LC
Oscillator 1
DPLL Output
OR
Gate
Local Oscillator
Phase Controller Divider
Injection LC
Remove Pulse Add Pulse Oscillator 2
The Proposed Oscillator
VIN
VOUT
n
f LO f IO
n 1
The Proposed Oscillator
Control period
Synchronization period
TC nt LO ( n 1 )t IO
1 1 2
TC ( n 1 )t LO nt IO t IO t t IO
n n n
1 1 2
TC ( n 1 )t LO ( n 2 )t IO t IO
n t t IO
n n
The Proposed Oscillator
2.00E-03
1.89E-03
1.80E-03
1.60E-03
frequency instability
1.40E-03
1.20E-03
1.00E-03
9.25E-04
8.00E-04
6.00E-04
4.00E-04
2.00E-04 1.98E-04
0.00E+00 3.04E-05
0 50 100 150 200 250 300
divider coefficient
r
W( S )
1 TC S
MATHEMATICAL MODEL
The Proposed Oscillator
Transfer function of the System kr( ST 1)
H (S ) .
3 2
S T C S T pkrT kr
S 2T (1 S C )
d lim SH ( S ) ( S )
H (S ) .
S 2 (1 S C ) k r( ST 1) S 0
2 T
( S ) 2 / S 3 ( S )
kr
Therefore, this type of PLL can trace a frequency ramp and therefore can be
used in the timing recovery and in space and satellite device
MATHEMATICAL MODEL
The Proposed Oscillator
Proportional
path
Incoming
signal Ring
Phase Code adder oscillator or
detector
LC tank
output
signal
Integral
path
divider
Local
Oscillator
+ Add-Remove Injected LC
Divider
Incoming signal Pluse oscillator
Phase Averaging -
detector Device
- +
Integral path
The value of overshoot is 78%, the number of oscillations in the period of control is
equal to 6. The setting time of the transition process is 0.00095s, the rising time is
3.4695e-006s, the Peak is 1.7759, and the Peak Time is 8.9127e-006 s.
These characteristics show that the simulated system is stable and has a margin
of stability in phase equal to 24.6, which corresponds to the requirements of
sustainability.
Phase Controller
Modeling in Verilog
Phase Detector
Implementation on FPGA
UP-Down Counter
Implementation on FPGA
Ideal Integrator
Implementation on FPGA
A new structure of a Bang- Bang Digital Phase Locked Loop BBDPLL is built.
The conventional digital PLL was modified in order to increase the operating
frequency.
AA Alsharef, MAM Ali, H Sanusi. Direct Digital Frequency Synthesizer Design and
Implementation on FPGA Research Journal of Applied Sciences Year: 2012 |
Volume: 7 | Issue: 8 | Page No.: 387-390.
AA Alsharef, Marvast, M. T., Ali, M. M., & Sanusi, H. 2011. A high speed and low
power voltage controlled ring oscillator for phase locked loop circuits. Proceedings
of the Micro and Nanoelectronics (RSM), 2011 IEEE Regional Symposium on, pp.
132-134.
AA Alsharef, MAM Ali, H Sanusi A Digital Controlled LC Oscillator with Output
Signal Generated via Frequency Transformation for High Speed Digital PLL (
preparing and writing)