DMA

Direct Memory Access

Introduction to 8237
 DMA Controller
A DMA controller interfaces with several peripherals that may request
DMA.

The controller decides the priority of simultaneous DMA requests

communicates with the peripheral and the CPU, and provides memory
addresses for data transfer.

DMA controller commonly used with 8086 is the 8237 programmable

device.

The 8237 is in fact a special-purpose microprocessor.

Normally it appears as part of the system controller chip-sets.

The 8237 is a 4-channel device. Each channel is dedicated to a specific

peripheral device and capable of addressing 64 K bytes section of
memory.
 Intel 8237A DMA Controller
Interfaces to 80x86 family and DRAM
When DMA module needs buses it sends HOLD signal to
processor
CPU responds HLDA (hold acknowledge)
DMA module can use buses
E.g. transfer data from memory to disk
1. Device requests service of DMA by pulling DREQ (DMA request) high
2. DMA puts high on HRQ (hold request),
3. CPU finishes present bus cycle (not necessarily present instruction)
and puts high on HDLA (hold acknowledge). HOLD remains active for
duration of DMA
4. DMA activates DACK (DMA acknowledge), telling device to start
transfer
5. DMA starts transfer by putting address of first byte on address bus and
activating MEMR; it then activates IOW to write to peripheral. DMA
decrements counter and increments address pointer. Repeat until
count reaches zero
6. DMA deactivates HRQ, giving bus back to CPU
 DMA
Some important signal pins:

DREQ3 DREQ0 (DMA request): Used to

request a DMA transfer for a particular DMA
channel.

DACK3 DACK0 (DMA channel

acknowledge): Acknowledges a channel
DMA request from a device.

HRQ (Hold request): Requests a DMA

transfer.

HLDA (Hold acknowledge) signals the

8237 that the microprocessor has
relinquished control of the address, data
and control buses.
 DMA

Some important signal pins:

A7 A4 : address pins are outputs that

provide part of the DMA transfer address
during a DMA operation.

DB0 DB7 : data bus, connected to

microprocessor and are used during the
programming DMA controller.
 Internal registers:
CAR : The current address register, is used to hold the 16-bit
memory address used for the DMA transfer.

CWCR : The current word count register, programs a channel for

the number of bytes (up to 64K) transferred during a DMA action.

BA & BWC : The base address and base word count , registers
are used when auto-initialization is selected for a channel. In this
mode, their contents will be reloaded to the CAR and CWCR after
the DMA action is completed.

The command register (CR) programs the operation of the

8237 DMA controller

Each channel has its own CAR, CWCR, BA and BWC.

 MR : The mode register, programs the mode of operation for a
channel. Each channels has its own mode register (RD/WR-INC/DEC..)

RR : The request register, is used to request a DMA transfer

via software, which is very useful in memory-to-memory
Transfers where external signals is not available for DMA transfer

MRSR : The mask register set/reset, sets or clears the channel

mask to disable or enable particular DMA channels. If the mask is set,
The channel is disabled

MSR : The mask register, clears or sets all of the masks with
one command instead of individual channels as with the
MRSR.

SR : The status register, shows the status of each DMA channel. TC

Bits indicate, terminal count
 Modes of Operation

Single Transfer Mode

In Single Transfer mode the device is programmed to make one
transfer only.

The word count will be decremented and the address

decremented or incremented following each transfer.

When the word count ``rolls over'' from zero to FFFFH, a

Terminal Count (TC) will cause an Auto initialize if the channel
has been programmed to do so.
Block Transfer Mode

In Block Transfer mode the device is activated by DREQ to

continue making transfers during the service until a TC, caused
by word count going to FFFFH, or an external End of Process
(EOP) is encountered.

DREQ need only be held active until DACK becomes active.

Again, an Autoinitialization will occur at the end of the service
if the channel has been programmed for it.
Demand Transfer Mode:
In Demand Transfer mode the device is programmed to continue
making transfers until a TC or external EOP is encountered or until
DREQ goes inactive.

Transfers may continue until the I/O device has exhausted its data
capacity. the DMA service can be re-established by means of a DREQ.

During the time between services when the microprocessor is

allowed to operate, the intermediate values of address and word
count are stored in the 8237A Current Address and Current Word
Count registers.

EOP can cause an Autoinitialize at the end of the service. EOP is

generated either by TC or by an external signal.
 DMA

Cascade Mode:
more than one 8237A
together for simple system
expansion.

The HRQ and HLDA signals

from the additional 8237A are
connected to the DREQ and
DACK signals of a channel of
the initial 8237A.

This allows the DMA requests

of the additional device to
propagate through the priority
network circuitry of the
preceding device.

Advanced Microprocessor 14