Semiconductor Memories

SEMICONDUCTOR
MEMORIES
Digital Integrated Circuits Memory Prentice Hall 1995

Chapter Overview
Memory Classification
Memory Architectures
The Memory Core
Periphery
Reliability

Semiconductor Memory
Classification
RWM NVRWM ROM
Random Non-Random EPROM Mask-Programmed

Access Access
E2PROM Programmable (PROM)
SRAM FIFO FLASH
DRAM LIFO
Shift Register
CAM

Memory Architecture: Decoders

Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
2L-K Bit Line

Storage Cell
AK
Row Decoder
AK+1 Word Line
AL-1
M.2K
Sense Amplifiers / Drivers Amplify swing to

rail-to-rail amplitude
A0
Column Decoder Selects appropriate
AK -1 word
Input-Output
(M bits)

Hierarchical Memory Architecture
Row
Address
Column
Address
Block
Address
Global Data Bus

Control Block Selector Global
Circuitry Amplifier/Driver
I/O
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings

Memory Timing: Definitions
Read Cycle
READ
Read Access Write Cycle

Read Access
WRITE
Write Access
Data Valid
DATA
Data Written

Memory Timing: Approaches
MSB LSB
Address
Row Address Column Address
Bus
RAS Address
Address
Bus
Address transition
CAS initiates memory operation
RAS-CAS timing
DRAM Timing SRAM Timing

Multiplexed Adressing Self-timed

MOS NOR ROM
VDD
Pull-up devices
WL[0]
GND
WL[1]
WL[2]
GND
WL[3]
BL[0] BL[1] BL[2] BL[3]

MOS NOR ROM Layout
Metal1 on top of diffusion
WL[0]
GND (diffusion)
WL[1]
Polysilicon
Basic cell
10 x 7 Metal1
WL[2] 2
WL[3]
Only 1 layer (contact mask) is used to program memory array

Programming of the memory can be delayed to one of
last process steps

MOS NOR ROM Layout
BL[0] BL[1] BL[2] BL[3]
Threshold raising
implant
WL[0]
GND (diffusion)
Basic Cell
8.5 x 7
Metal1 over diffusion
WL[1]
Polysilicon
WL[2]
WL[3]
Threshold raising implants disable transistors

MOS NAND ROM
V DD
Pull-up devices
BL[0] BL[1] BL[2] BL[3]
WL[0]
WL[1]
WL[2]
WL[3]
All word lines high by default with exception of selected row

MOS NAND ROM Layout
Diffusion
Polysilicon
Basic cell
5x 6
Threshold
lowering
implant
No contact to VDD or GND necessary;

drastically reduced cell size
Loss in performance compared to NOR ROM

Equivalent Transient Model for MOS NOR
ROM
VDD
BL
rword
Model for NOR ROM WL
Cbit
cword
Word line parasitics

Resistance/cell: (7/2) x 10 /q = 35
Wire capacitance/cell: (7 2) (0.6)2 0.058 + 2 (7 0.6) 0.043 = 0.65 fF
Gate Capacitance/cell: (4 2) (0.6)2 1.76 = 5.1 fF.
Bit line parasitics:
Resistance/cell: (8.5/4) x 0.07 /q = 0.15 (which is negligible)
Wire capacitance/cell: (8.5 4) (0.6)2 0.031 + 2 (8.5 0.6) 0.044 = 0.83 fF
Drain capacitance/cell: ((3 4) (0.6)2 0.3 + 2 3 0.6 0.8) 0.375 +
4 0.6 0.43 = 2.6 fF

Equivalent Transient Model for MOS NAND
ROM
VDD
BL
CL
rbit
Model for NAND ROM
rword cbit
WL
cword
Word line parasitics:

Resistance/cell: (6/2) x 10 /q = 30
Wire capacitance/cell: (6 2) (0.6)2 0.058 + 2 (6 0.6) 0.043 = 0.56 fF
Gate Capacitance/cell: (3 2) (0.6)2 1.76 = 3.8 fF.
Bit line parasitics:
Resistance/cell: 10 k, the average transistor resistance over the range of interest.
Wire capacitance/cell: Included in diffusion capacitance
Source/Drain capacitance/cell: ((3 3) (0.6)2 0.3 + 2 3 0.6 0.8) 0.375 + ( ) (0.6)2
1.76 = 5.2 fF

Propagation Delay of NOR ROM
Word line delay
Consider the 512512 case. The delay of the distributed rc-line containing M
cells can be approximated using the expressions derived in Chapter 8.
tword = 0.38 (rword cword ) M2 = 0.38 (35 (0.65 + 5.1) fF) 5122 = 20 nsec
Bit line delay

Assume a (2.4/1.2) pull-down device and a (8/1.2) pull-up transistor. The bit
line switches between 5 V and 2.5 V.
Cbit = 512 (2.6 + 0.8) fF = 1.7 pF
IavHL = 1/2 (2.4/0.9) (19.6 10 -6)((4.25)2/2 + (4.25 3.75 - (3.75)2/2)) -

1/2 (8/0.9) (5.3 10 -6) (4.25 1.25 - (1.25)2/2) = 0.36 mA
tHL = (1.7 pF 1.25 V) / 0.36 mA = 5.9 nsec
The low-to-high response time can be computed using a similar approach.
tLH = (1.7 pF 1.25 V) / 0.36 mA = 5.9 nsec

Decreasing Word Line Delay
Driver
WL Polysilicon word line
Metal word line
(a) Driving the word line from both sides
Metal bypass
WL K cells Polysilicon word line
(b) Using a metal bypass
(c) Use silicides

Precharged MOS NOR ROM
VDD
pre
Precharge devices
WL[0]
GND
WL[1]
WL[2]
GND
WL[3]
BL[0] BL[1] BL[2] BL[3]
PMOS precharge device can be made as large as necessary,

but clock driver becomes harder to design.

Floating-gate transistor (FAMOS)
Floating gate Gate

D
Source Drain
tox G
tox
S
+ p +
n n
Substrate
(a) Device cross-section (b) Schematic symbol

Floating-Gate Transistor Programming
20 V 0V 5V
20 V 0V 5V
10 V 5 V 5 V 2.5 V
S D S D S D
Avalanche injection. Removing programming voltage Programming results in

leaves charge trapped. higher V T.

FLOTOX EEPROM
Floating gate Gate I
Source Drain
20-30 nm 10 V VGD
10 V
n+ n+
Substrate
p
10 nm
(a) Flotox transistor (b) Fowler-Nordheim I-V characteristic

BL
WL
V DD
(c) EEPROM cell during a read operation

Flash EEPROM
Control gate
Floating gate
erasure Thin tunneling oxide
n+ source n+ drain
programming
p-substrate

Cross-sections of NVM cells
Flash Courtesy Intel

EPROM
Characteristics of State-of-the-art
NVM

Read-Write Memories (RAM)
STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential
DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
6-transistor CMOS SRAM Cell
WL
VDD
M2 M4
Q
Q M6
M5
M1 M3
BL BL

CMOS SRAM Analysis (Write)
WL
VDD
M4
Q=0 M6
M5 Q=1
M1
VDD
BL = 1 BL = 0
VDD VDD 2
k n M6 VDD VTn ----------- ----------
VDD VDD 2
- = k p M4 VDD VTp ----------- ----------
- (W/L)n,M60.33 (W/L)p,M4
2 8 2 8
kn M5 V VDD 2 V DD V 2
-------------- ----------
DD
- V ----------
- = k V V ---------- DD
- ----------- (W/L)n,M5 10 (W/L)n,M1
2 2 Tn 2 n M1 DD Tn 2 8

CMOS SRAM Analysis (Read)
WL
VDD
BL M4
BL
Q= 0 M6
M5 Q=1
M1 V DD
V DD V DD
Cbit C bit
kn M5 V VD D 2 VDD V 2
--------------- -----------
DD- V -----------
- = k V V D D-
------------ -----------
2 2 Tn 2 n M1 D D Tn 2 8
(W/L)n,M510 (W/L)n,M1 (supercedes read constraint)

6T-SRAM Layout
M2 M4
VDD
Q Q
M1 M3
GND
M5 M6 WL
BL BL

Resistance-load SRAM Cell
WL
VDD
RL RL
Q Q
M3 M4
BL M1 M2 BL
Static power dissipation -- Want RL large

Bit lines precharged to VDD to address t p problem

3-Transistor DRAM Cell
BL1 BL2
WWL WWL
RWL
RWL
X VDD -VT
X M3
M2
M1 VDD
BL1
CS
BL2 VDD -VT V
No constraints on device ratios

Reads are non-destructive
Value stored at node X when writing a 1 = VWWL -VTn

3T-DRAM Layout
BL2 BL1 GND
RWL
M3
M2
WWL
M1

1-Transistor DRAM Cell
BL
WL Write "1" Read "1"
WL
M1 CS X GND VDD VT
VDD
BL
VDD/2 VDD /2
CBL sensing
Write: CS is charged or discharged by asserting WL and BL.

Read: Charge redistribution takes places between bit line and storage capacitance
CS
V = VBL V PRE = V BIT V PRE ------------------------
C S + CBL
Voltage swing is small; typically around 250 mV.

DRAM Cell Observations
1T DRAM requires a sense amplifier for each bit line, due to

charge redistribution read-out.
DRAM memory cells are single ended in contrast to SRAM cells.
The read-out of the 1T DRAM cell is destructive; read and
refresh operations are necessary for correct operation.
Unlike 3T cell, 1T cell requires presence of an extra capacitance
that must be explicitly included in the design.
When writing a 1 into a DRAM cell, a threshold voltage is lost.
This charge loss can be circumvented by bootstrapping the
word lines to a higher value than VDD .

1-T DRAM Cell
Capacitor
Metal word line

M1 word
SiO2 line
poly
Field Oxide
n+ n+
Inversion layer Diffused
poly
induced by bit line
plate bias
Polysilicon
Polysilicon
plate
(a) Cross-section gate
(b) Layout
Used Polysilicon-Diffusion Capacitance

Expensive in Area
SEM of poly-diffusion capacitor 1T-DRAM

Advanced 1T DRAM Cells
Word line
Cell plate Capacitor dielectric layer
Insulating Layer
Cell Plate Si
Capacitor Insulator Transfer gate Isolation

Refilling Poly Storage electrode
Storage Node Poly
Si Substrate
2nd Field Oxide
Trench Cell Stacked-capacitor Cell

Periphery
Decoders
Sense Amplifiers
Input/Output Buffers
Control / Timing Circuitry

Row Decoders
Collection of 2M complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder

Dynamic Decoders
Precharge devices GND GND
VDD
WL3
WL 3 VDD
WL2
WL 2 VDD
WL 1 WL1
VDD
WL 0 WL0
V DD A0 A0 A1 A1 A0 A0 A1 A1
Dynamic 2-to-4 NOR decoder 2-to-4 MOS dynamic NAND Decoder
Propagation delay is primary concern

A NAND decoder using 2-input pre-
decoders
WL 1
WL 0
A0A1 A0 A1 A0 A1 A0A 1 A 2A3 A2 A3 A2 A3 A2 A3
A1 A 0 A0 A1 A3 A2 A2 A3
Splitting decoder into two or more logic layers

produces a faster and cheaper implementation
4 input pass-transistor based column
decoder
BL0 BL1 BL2 BL3
S0
A0 2 input NOR decoder
S1
S2
A1
S3
D
Advantage: speed (tpd does not add to overall memory access time)
only 1 extra transistor in signal path
Disadvantage: large transistor count
4-to-1 tree based column decoder
BL0 BL1 BL2 BL3
A0
A0
A1
A1
D
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
Solutions: buffers
progressive sizing
combination of tree and pass transistor approaches

Decoder for circular shift-register
VDD VDD VDD VDD VDD VDD
WL0 WL1 WL2

...
R R R
VDD

Sense Amplifiers
make V as small
C V as possible
tp = ----------------
Iav
large small
Idea: Use Sense Amplifer
small
transition s.a.
input output

Differential Sensing - SRAM
VDD VDD
VDD PC VDD
y M3 M4 y
x M1 M2 x x x
BL BL
EQ
SE M5 SE
WLi
(b) Doubled-ended Current Mirror Amplifier
VDD
SRAM cell i
y y
Diff.
x Sense x x x
Amp
y y
D D SE
(a) SRAM sensing scheme.

(c) Cross-Coupled Amplifier

Latch-Based Sense Amplifier
EQ
BL BL
VDD
SE
SE
Initialized in its meta-stable point with EQ

Once adequate voltage gap created, sense amp enabled with SE
Positive feedback quickly forces output to a stable operating point.
Single-to-Differential Conversion
WL
BL
x Diff. x
+
cell S.A. _ Vref
y y
How to make good V ref?

Open bitline architecture
EQ
R L1 L0 R0 R1 L
VDD
SE
BLL BLR
... ...
CS CS CS SE CS CS CS
dummy dummy
cell cell

DRAM Read Process with Dummy Cell
6.0
4.0
V (Volt)
BL
2.0 BL
5.0
0.00 4.0 WL
1 2 3 4 5
V (Volt)
t (nsec) 3.0 SE
(a) reading a zero
2.0 EQ
6.0
1.0
0.00 1 2 3 4 5
4.0
V (Volt)
(c) control signals

BL
2.0 BL
0.00 1 2 3 4 5
t (nsec)
(b) reading a one

Single-Ended Cascode Amplifier
VDD
Vcasc
WLC
WL

DRAM Timing

Address Transition Detection
VDD
DELAY
A0 td
ATD ATD
DELAY
A1 td
...
DELAY
AN-1 td

Reliability and Yield

Open Bit-line Architecture Cross Coupling
EQ
WL1 WL0 WLD WLD WL0 WL1

CWBL CWBL
BL BL
Sense
CBL CBL
Amplifier
C C C C C C

Folded-Bitline Architecture
WL1 WL1 WL0 WL0 WLD WLD

CWBL
BL CBL x y
... Sense
C C C C C C
EQ Amplifier
BL CBL x y
CWBL

Transposed-Bitline Architecture
BL
Ccross
BL
SA
BL
BL"
(a) Straightforward bitline routing.
BL
Ccross
BL
SA
BL
BL"
(b) Transposed bitline architecture.

Alpha-particles
-particle
WL
VDD
BL
SiO2
n+
1 particle ~ 1 million carriers

Yield
Yield curves at different stages of process maturity

(from [Veendrick92])
Redundancy
Row
Address
Redundant
rows
Fuse
:
Bank
Redundant
columns
Row Decoder
Memory
Array
Column
Column Decoder
Address

Redundancy and Error Correction

Programmable Logic Array
Product Terms
x0x1
AND
x2 OR
PLANE PLANE
f0 f1
x0 x1 x2

Pseudo-Static PLA
VD D
GND GND GND GND
GND
GND
GND
VDD f0 f1
x0 x0 x1 x1 x2 x2
AND-PLANE OR-PLANE

Dynamic PLA
A ND
GND VDD
OR
O R
AND
VDD f0 f1 GND
x0 x0 x1 x1 x2 x2
AND-PLANE OR-PLANE

Clock Signal Generation
for self-timed dynamic PLA
AND
Dummy AND Row
AND
AND OR
Dummy AND Row
OR
(a) Clock signals (b) Timing generation circuitry.

PLA Layout
And-Plane Or-Plane
VDD GND
x0 x0 x1 x1 x2 x2 f0 f1
Pull-up devices Pull-up devices
PLA versus ROM
Programmable Logic Array

structured approach to random logic
two level logic implementation
NOR-NOR (product of sums)
NAND-NAND (sum of products)
IDENTICAL TO ROM!
Main difference
ROM: fully populated
PLA: one element per minterm
Note: Importance of PLAs has drastically reduced

1. slow
2. better software techniques (mutli-level logic
synthesis)

Semiconductor Memory Trends
Memory Size as a function of time: x 4 every three years

Increasing die size

factor 1.5 per generation
Combined with reducing cell size
factor 2.6 per generation

Technology feature size for different SRAM generations

Semiconductor Memories

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SEMICONDUCTOR

Digital Integrated Circuits Memory Prentice Hall 1995

The Memory Core

Digital Integrated Circuits Memory Prentice Hall 1995

RWM NVRWM ROM

Random Non-Random EPROM Mask-Programmed

SRAM FIFO FLASH

Digital Integrated Circuits Memory Prentice Hall 1995

Digital Integrated Circuits Memory Prentice Hall 1995

2L-K Bit Line

AK+1 Word Line

Sense Amplifiers / Drivers Amplify swing to

Digital Integrated Circuits Memory Prentice Hall 1995

Global Data Bus

Digital Integrated Circuits Memory Prentice Hall 1995

Read Access Write Cycle

Digital Integrated Circuits Memory Prentice Hall 1995

DRAM Timing SRAM Timing

Digital Integrated Circuits Memory Prentice Hall 1995

BL[0] BL[1] BL[2] BL[3]

Digital Integrated Circuits Memory Prentice Hall 1995

Only 1 layer (contact mask) is used to program memory array

Digital Integrated Circuits Memory Prentice Hall 1995

Threshold raising implants disable transistors

Digital Integrated Circuits Memory Prentice Hall 1995

BL[0] BL[1] BL[2] BL[3]

All word lines high by default with exception of selected row

Digital Integrated Circuits Memory Prentice Hall 1995

No contact to VDD or GND necessary;

Digital Integrated Circuits Memory Prentice Hall 1995

Word line parasitics

Digital Integrated Circuits Memory Prentice Hall 1995

Word line parasitics:

Digital Integrated Circuits Memory Prentice Hall 1995

Bit line delay

Cbit = 512 (2.6 + 0.8) fF = 1.7 pF

IavHL = 1/2 (2.4/0.9) (19.6 10 -6)((4.25)2/2 + (4.25 3.75 - (3.75)2/2)) -

The low-to-high response time can be computed using a similar approach.

tLH = (1.7 pF 1.25 V) / 0.36 mA = 5.9 nsec

Digital Integrated Circuits Memory Prentice Hall 1995

Metal word line

(a) Driving the word line from both sides

WL K cells Polysilicon word line

(b) Using a metal bypass

(c) Use silicides

BL[0] BL[1] BL[2] BL[3]

PMOS precharge device can be made as large as necessary,

Digital Integrated Circuits Memory Prentice Hall 1995

Floating gate Gate

(a) Device cross-section (b) Schematic symbol

Digital Integrated Circuits Memory Prentice Hall 1995

Avalanche injection. Removing programming voltage Programming results in

Digital Integrated Circuits Memory Prentice Hall 1995

(a) Flotox transistor (b) Fowler-Nordheim I-V characteristic

(c) EEPROM cell during a read operation

Digital Integrated Circuits Memory Prentice Hall 1995

erasure Thin tunneling oxide

Digital Integrated Circuits Memory Prentice Hall 1995

Flash Courtesy Intel

Digital Integrated Circuits Memory Prentice Hall 1995

Digital Integrated Circuits Memory Prentice Hall 1995

Digital Integrated Circuits Memory Prentice Hall 1995

(W/L)n,M510 (W/L)n,M1 (supercedes read constraint)

Digital Integrated Circuits Memory Prentice Hall 1995