Interrupts of 8051
5th Semester
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Inside Architecture of 8051
External interrupts
On-chip R Timer/Counter
Interrupt OM for pr
On-chip Timer 1 Counter
Control ogram co
RAM Timer 0 Inputs
de
CPU
P0 P1 P2 P3 TxD RxD
Address/Data
8051 Microcontroller Block Diagram
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I/O Services
3
Polling method
4
Interrupt method
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The advantage of Interrupts
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Interrupt Service Routine
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Table 11-1: Interrupt Vector Table for the 80
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Reset 0000 9
P3.2
External hardware interrupt 0 (INT0) 0003
(12)
Timer 0 interrupt (TF0) 000B
P3.3
External hardware interrupt 1 (INT1) 0013
(13)
Timer 1 interrupt (TF1) 001B
Serial COM interrupt (RI and TI) 0023 8
Six Interrupts in the 8051
Reset
Two interrupt for the timers
TF0, TF1
Two interrupt for external hardware interrupts
INT0, INT1
Serial communication
TI or RI
There is a limited number of bytes for each interrupt.
3 bytes for reset
8 bytes for timers and external hardware interrupts
If the service routine is too short to fit the ISR, an LJMP instruction is placed i
n the vector table to point to the address of the ISR.
Programmers must enable these interrupts before using them.
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IE (Interrupt Enable) Register
EA IE.7 Disables all interrupts.
If EA=0, no interrupt is acknowledged.
If EA=1, each interrupt source is individually enabled of
disabled by setting or clearing its enable bit.
--- IE.6 Not implemented, reserved for future use. *
ET2 IE.5 Enables or disables timer 2 overflow or capture interrupt
(8952).
ES IE.4 Enables or disables the serial port interrupt. RI or TI
ET1 IE.3 Enables or disables timer 1 overflow interrupt. TF1
EX1 IE.2 enables or disables external interrupt 1. INT1
ET0 IE.1 Enables or disables timer 0 overflow interrupt. TF0
EX0 IE.0 enables or disables external interrupt 0. INT0 10
Steps in Enabling an Interrupt
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External Hardware Interrupts
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External Hardware Interrupts
13
THANK YOU
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