MOS Field-Effect

Transistors (MOSFETs)

1
 Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 mm, W = 0.2 to
100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 2
 Ingat pada p-n junction

Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at
the top of the substrate beneath the gate.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 3
 Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is
determined by vGS. Specifically, the channel conductance is proportional to vGS Vt and thus iD is proportional to (vGS Vt) vDS.
Note that the depletion region is not shown (for simplicity).

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 4
 Figure 4.4 The iDvDS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, vDS,
is kept small. The device operates as a linear resistor whose value is controlled by vGS.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 5
 Figure 4.5 Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered
shape, and its resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 6
 Figure 4.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated
with vGS > Vt.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 7
 Figure 4.7 Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS reaches vGS Vt the channel is
pinched off at the drain end. Increasing vDS above vGS Vt has little effect (theoretically, no effect) on the channels shape.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 8
 Equipotential pada arah y (melebar)
Kapasitansi gate-channel
(dielektrik SiO2) per
satuan area (1)

Cox ox
tox

(2)

Muatan tersimpan dalam

Kapasitor (3)
Q CV

Muatan tersimpan dalam

potongan equipotensial
(4)
Figure 4.8 Derivation of the iDvDS characteristic of the NMOS transistor. dq Cox W dx vGS v( x) Vt
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 9
 Muatan pada celah potongan dq Cox W dx vGS v( x) Vt sehingga

Cox W vGS v( x) Vt
dq
dx

Medan listrik pada

potongan
dvx
E x
dx

Laju elektron (drift)

Karena medan listrik
dv x
mn E x mn
dx
dt dx

Arus drift pada celah potongan

dq dq dx
i
dt dx dt
dvx
Figure 4.8 Derivation of the iDvDS characteristic of the NMOS transistor. i mn Cox W vGS v( x) Vt
dx
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 10
 Arus drain yang disebabkan arus drift pada celah potongan
dv x
iD i mn Cox W vGS v( x) Vt
dx
dapat disusun menjadi

iD dx mn Cox W vGS v( x) Vt dvx

Integrasi dengan batas source

dan drain atau x antar 0 dan L
dan tegangan 0 dan vDS
L v DS

iD dx mn Cox W vGS v( x) Vt dvx

0 0

memberikan
W 1 2
iD mn Cox vGS Vt v DS vDS
L 2

Untuk saturasi vDsat vGS Vt arus drain menjadi iD

1
mn Cox W vGS Vt 2
2 L

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 11
 iD
1
mn Cox W vGS Vt 2
2 L
1 W
iD k n' vGS Vt 2
2 L

W 1 2
iD m n Cox v GS Vt v DS vDS definisi konstanta
L 2
W 1 2 kn' mn Cox
iD kn' v V v vDS
L
GS t DS
2
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 12
 Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type
region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is
formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the
body terminal for the p-channel device.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 13
 Potongan
melintang

Layout

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 14
 Perhatikan:
arah panah menunjukkan arah junction seperti pada dioda
Kanal tipe n dan bodi tipe p

Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with an
arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c)
Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device
operation is unimportant.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 15
 Perilaku arus-tegangan MOSFET dan Daerah Operasinya

Pengukuran/ Karakterisasi

Figure 4.11 (a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of
current flow indicated. (b) The iDvDS characteristics for a device with kn (W/L) = 1.0 mA/V2.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 16
 Daerah Trioda
Syarat
1. kanal terbentuk vGS Vt
2. Kanal kontinyu

Bentuk Kanal

Kanal kontinyu atau tegangan gate-drain masih

membentuk kanal (daerah deplesi belum
terlalu besar sehingga membuat kanal
Pinch-off) Persamaan arus-tegangan
vGD Vt
W 1 2
iD kn' v V v vDS
atau vDS vGS Vt L
GS t DS
2

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 17
 Daerah Trioda
Persamaan arus-tegangan
W 1 2
iD kn' vGS V t v DS vDS
L 2
untuk vDS 2vGS Vt

menjadi iD kn'
W
vGS Vt vDS
L
dapat dinyatakan sebagai
1
W
kn' vGS Vt
v
rDS DS
iD v DS kecil L
v GS VGS

Dengan definisi VOV VGS Vt

1
menjadi rDS
W
kn' VOV Mengapa DS
L huruf kapital?
syarat vDS 2VOV
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 18
 Daerah Saturasi
Syarat
1. kanal terbentuk vGS Vt
2. Pinch-off

Bentuk Kanal

Kanal pinch-off, tegangan gate-drain tidak

lagi membentuk kanal, arus drain hanya
ditentukan jumlah muatan yang dibentuk
tegangan gate pada kanal
Persamaan arus-tegangan
vGD Vt

k n vGS Vt
vDS vGS Vt 1 'W
iD
2
atau
2 L

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 19
 Daerah Saturasi

Persamaan arus-tegangan

k n vGS Vt
1 'W
iD
2

2 L

Untuk drain-gate terhubung

singkat

vDS vGS

MOSFET selalu saturasi

karena Vt 0
1 'W
iD
2
kn vDS
2 L

Figure 4.12 The iDvGS characteristic for an enhancement-type NMOS transistor in saturation (Vt = 1 V, kn W/L = 1.0
mA/V2).

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 20
 Figure 4.13 Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation region.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 21
 Figure 4.14 The relative levels of the terminal voltages of the enhancement NMOS transistor for operation in the triode
region and in the saturation region.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 22
 Setelah mencapai saturasi apabila tegangan drain-source
masih dinaikkan, maka panjang kanal berkurang
Persamaan arus semula
k n vGS Vt
1 'W
iD
2

2 L
menjadi
iD
1 ' W
kn vGS Vt 2
2 L L
disusun ulang
iD
1 'W
kn
1
vGS Vt 2
2 L 1 L / L

untuk L / L 1 dapat didekati dengan

1 W
iD k n' 1 L / L vGS Vt 2
2 L
L / L sebanding dengan vDS

dan dapat dinyatakan dengan L vDS sehingga

L
k n 1 vDS vGS Vt
1 'W
iD
2

2 L
Figure 4.15 Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus
reducing the effective channel length (by DL).

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 23
 k n 1 vDS vGS Vt
1 'W
iD
2

2 L
1
untuk iD 0 maka VA
ID

1 1

Definisikan ro iD
1 W
maka ro k n' VGS Vt 2
vDS vGS tetap 2 L

k n VGS Vt
1 VA 1 'W
sehingga ro atau ro ID
2
dimana
ID ID 2 L

Figure 4.16 Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the process technology
and, for a given process, is proportional to the channel length L.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 24
 VA
ro
ID

k n VGS Vt
1 'W
ID
2

2 L

Figure 4.17 Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output
resistance ro. The output resistance models the linear dependence of iD on vDS and is given by Eq. (4.22).

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 25
 Daerah Trioda
Syarat
1. kanal terbentuk vSG Vt
2. Kanal kontinyu vDS vGS Vt

Persamaan arus-tegangan
W 1 2
iD k p' vGS Vt v DS vDS
L 2
dengan k p' m pCox

Daerah Saturasi
Syarat
1. kanal terbentuk
2. Pinch-off vDS vGS Vt
Persamaan arus-tegangan

k p vGS Vt
1 ' W
iD
2

2 L
Figure 4.18 (a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Modified symbol with an arrowhead on the source
lead. (c) Simplified circuit symbol for the case where the source is connected to the body. (d) The MOSFET with voltages applied and
the directions of current flow indicated. Note that vGS and vDS are negative and iD flows out of the drain terminal.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 26
 Figure 4.19 The relative levels of the terminal voltages of the enhancement-type PMOS transistor for operation in the triode region
and in the saturation region.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 27
 Vt=-1V, kp=60mA/V2, W/L=10, hitung
(a) VG agar FET konduksi
(b) VD untuk triode
(c) VD untuk saturasi
(d) untuk =0, |VOV|, VG dan VD untuk ID=75mA
(e) ro untuk =-0,02V-1 dan |VOV| dari (d)
(f) ID untuk =-0,02V-1 dan |VOV| dari (d) pada VD=+3V
dan VD=0V, lalu hitung ro dan bandingkan dengan (e)

(a) Syarat vSG Vt VG VS Vt VG 5 1 4V

(b) Syarat vDS vGS Vt VD VG Vt VD VG 1

(c) Syarat vDS vGS Vt VD VG Vt VD VG 1

Figure E4.8

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 28
 (d) Asumsi saturasi
75m
1 W
I D kn' VOV VOV
2 ID VOV 0,5V
1
2 L 1 ' W
kp 60m 10
2 L 2

VOV VSG Vt VSG VOV Vt VSG 0,5 1 1,5V

VSG VS VG VG VS VSG VSG 5 1,5 3,5V

VDS VGS Vt VD VG Vt VD 3,5 (1) 4,5V

1 1
(e) ro 0,667 M
I D 0,02 75m
k p 1 vDS VOV iD 1 vDS 75m
1 ' W
iD
2
(f) Untuk ini
2 L
VD 3V iD 1 0,02 3 575m 78mA
VD 0V iD 1 0,02 0 575m 82,5mA
V V 25
ro DS1 DS 2 M 0,667 M sama!
Figure E4.8
I D1 I D 2 78 82,5

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 29
 Table 4.1

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 30
 Body Effect pada tegangan threshold

Vt Vt 0 2 f VSB 2 f
2qN A s

Cox

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 31
 ID diinginkan 400mA, VD =0,5V, RD dan RS?
Vt=0,7V, mnCox=100mA/V2, L=1mm, dan W=32mm

Langkah:
1. Cek konduksi? Cek saturasi atau triode?
2. Hitung VOV
3. Hitung VGS
4. Hitung VS

Figure 4.20 Circuit for Example 4.2.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 32
 ID diinginkan 80mA, R?
Vt=0,6V, mnCox=200mA/V2, L=0,8mm, dan W=4mm

MOSFET dalam keadaan saturasi (mengapa?)

iD
1
mn Cox W vGS Vt 2 1 mn Cox W VOV 2
2 L 2 L

2I D 2 80
VOV 0,4V
W 4
m nCox 200
L 0,8

VGS VOV Vt 0,4 0,6 1V VD VGS 1V

VDD VD 3 1
R 25k
ID 80m

Figure 4.21 Circuit for Example 4.3.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 33
 Rangkaian pada cabang kanan idem rangkaian sebelumnya,
berapa arus pada R=20k? Berapa tegangan drain?
FET Q2 dan Q1 identik

Anggap saturasi, VOV pada kedua rangkaian sama,

maka arus sama, yaitu 80mA

VD VDD I D R2 3 80m 20k 1,4V

Tegangan VDS=VD>VOV
maka FET Q2 dalam keadaan saturasi (anggapan benar)

Figure E4.12

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 34
 Rancang agar VD = 0,1V (atau RD?)
Vt=1V, knW/L=1mA/V2

FET dalam keadaan trioda, karena

sehingga

W 1 2
iD kn' vGS Vt v DS vDS
L 2

I D 1 5 1 0,1 0,12 0,395mA
1
2

VDD VD 5 0,1
R 12,4k
ID 395m

Mengikuti nilai resistor baku yang tersedia untuk

Toleransi 5% dapat digunakan 12k

Figure 4.22 Circuit for Example 4.4.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 35
 Figure 4.23 (a) Circuit for Example 4.5. (b) The circuit with some of the analysis details shown.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 36
 Figure 4.24 Circuit for Example 4.6.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 37
 Figure 4.25 Circuits for Example 4.7.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 38
 Figure E4.16

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 39
 VDD 1
iD vDS
RD RD

vO vDS VDD RD iD

Fungsi R?

Figure 4.26 (a) Basic structure of the common-source amplifier. (b) Graphical construction to determine the transfer characteristic of
the amplifier in (a).

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 40
 Figure 4.26 (Continued) (c) Transfer characteristic showing operation as an amplifier biased at point Q.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 41
 Figure 4.27 Two load lines and corresponding bias points. Bias point Q1 does not leave sufficient room for positive signal
swing at the drain (too close to VDD). Bias point Q2 is too close to the boundary of the triode region and might not allow for
sufficient negative signal swing.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 42
 MOSFET saturasi

iD
1
m n Cox W vI Vt 2
2 L

vO VDD RD iD

vO VDD RD m n Cox vI Vt
1 W 2

2 L

Av
dvO
dvI
Av RD m n Cox
W
VIQ Vt
vI VIQ
L

VOB VIB Vt

dv 2VDD VOQ 2VRD VOV VIQ Vt

Av O Av
dvI vO VOQ
VOV VOV

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 43
 MOSFET triode

W 1 2
iD m n Cox
Iv Vt vO vO
L 2

vO VDD RD iD

vO VDD RD m n Cox vI Vt vO
W
L
VDD
vO
1 RD m n Cox vI Vt
W
L
1
atau dengan rDS
m n Cox W vI Vt
L
rDS
vO VDD
rDS RD
rDS
untuk rDS RD maka vO VDD
RD
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 44
 Contoh Numerik
kn(W/L)=1mA/V2 Vt=1V VDD=10V RD=18k

Letak X vI 0V vO VDD 10V

Letak A vI Vt 1V vO VDD 10V

Letak B vI VIB VOB Vt VOB 1

vO VDD RD m n Cox vI Vt
1 W 2

2 L
VOB VDD RD m n Cox VIB Vt
1 W 2

2 L
1
VOB 10 18 1 VOB
2

2
9VOB VOB 10 0
2

(9VOB 10)(VOB 1) 0 VOB 1V

VIB 2V

Letak C 1
1 1 rDS
rDS VOC VDD 10 9 0,061V
m n Cox W vI Vt 1 10 1 rDS RD 1 18
9
L
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 45
 Contoh Numerik

Letak Q 10V

Q dapat dipilih tepat diantara jangkauan

tegangan output atau 5,5V namun untuk
mendapat gain yang lebih besar dipilih
5,5V
pada tegangan output 4V
4V
VOQ 4V
VDD VOQ 10 4 1 2V
ID mA
RD 18k 3
1 W 2
I D k n' VOV
2 L
2I D 2 1 / 3
VOV 0,816V
' W 1
kn
L
VIQ VGSQ VOV Vt 0,816 1 1,816V

Av RD m n Cox
W
VIQ Vt 18 1 1,816 1 14,7V / V
L

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 46
 Contoh Numerik

Tegangan input

Figure 4.28 Example 4.8.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 47
 k n vGS Vt vO VDD iD RD
vI vGS 1 'W
iD
2

2 L

[V ]
1
vGS 12 [mA] 10 18iD [V ]
2
1,741 0,275 5,05

1,816 0,333 4,00

1,891 0,397 2,85

Figure 4.28 (Continued)

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 48
 Contoh dengan SPICE
Rangkaian Amplifier Sederhana dengan MOSFET Example 4.8
*
* Rangkaiannya
*
* FETnya FET drain gate source body nama_model
*
M1 out in 0 0 NMOS1 L=1u W=1u
*
* Resistor drain RD=18k
*
R1 vdd out 18k
*
* Power Supply VDD=10V
*
VDD vdd 0 10
*
* Tegangan Input Sinusoidal DC 1.816V Amplitude AC 77mV Frekuensi 10KHz
* Alternatif untuk sinyal seperti dalam teks menggunakan PWL
*
*VS in 0 SIN(1.816 0.075 10k 0 0)
VS in 0 PWL(0 1.816 50us 1.741 150us 1.891 250us 1.741 350us 1.891 450us 1.741 500us 1.816)
*
.MODEL NMOS1 NMOS KP=1e-3 VTO=1
.end
.control
tran 5us 0.5ms
plot in out
plot out vs in
.end

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 49
 Contoh dengan SPICE

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 50
 Pemberian Bias Penguat MOSFET

Cara paling sederhana dengan memberikan

tegangan tetap (DC) langsung antara terminal
gate dan source VGS

Cara ini kurang tepat mengingat mobilitas

pembawa muatan dan tegangan threshold
fungsi (kuat) temperatur sehingga dapat
memberikan arus drain yang berbeda pula
seperti ditunjukkan pda kurva ini

iD
1
mn Cox W vGS Vt 2
2 L
W 1 2
iD m n Cox vGS Vt vDS vDS
L 2

Figure 4.29 The use of fixed bias (constant VGS) can result in a large variability in the value of ID. Devices 1 and 2
represent extremes among units of the same type.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 51
 VG VGS RS I D

Figure 4.30 Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS: (a) basic
arrangement; (b) reduced variability in ID; (c) practical implementation using a single supply; (d) coupling of a signal
source to the gate using a capacitor CC1; (e) practical implementation using two supplies.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 52
 Contoh
kn(W/L)=1mA/V2 Vt=1V VDD=15V
Hitung (rancang) nilai resistansi yang diperlukan
untuk ID=0,5mA Apayang terjadi bila Vt naik menjadi 1,5V?
1. Gunakan thumb rule untuk menen- 2
tukan tegangan drain-source
1 1 1
VDS VDD VS VDD VDD VD VDD 1
3 3 3
1 1
VS 15 5V VD 15 5V
3 3 3 1
2. Hitung resistor di source dan drain
2
VS 5
RS 10k
I D 0,5m
VDD VD 15 10
RD 10k
ID 0,5m
2I D 2 0,5
3. Hitung tegangan overdrive yang diperlukan VOV 1V
W 1
kn'
Figure 4.31 Circuit for Example 4.9. L

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 53
 Contoh
4. Hitung tegangan gate-source
VGS VOV Vt 1 1 2V

5. Hitung tegangan gate 6 2

VG VGS VS 2 5 7V
1
6. Hitung (pilih) resistor pembagi tegangan gate 5

RB
VG VDD 4
3
RB RA 1

RB
7 15 6 2
RB RA

RB 7M RA 8M

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 54
 Contoh
Tegangan threshold naik menjadi 1,5V
1. Tegangan gate tetap VG 7V

2. Gunakan rangkaian di source untuk

menentukan tegangan gate-source
VG VGS RS I D
7 VGS 10I D VGS 7 10I D 1
3
3. Gunakan persamaan arus-tegangan
FET untuk menentukan arus drain

k n VGS Vt
1 'W 2
ID
2

2 L
I D VGS 1,5
1 2
I D
1
7 10 I D 1,52
2 2
50I D2 54I D 15,125 0 I D 0,455mA

Perubahan arus drain I D I D1 I D2 0,455 0,5 0,045mA

atau I D 0,045
100% 9%
ID 0,5
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 55
 VDD VGS RD I D

VGS VDS VDD RD I D

Figure 4.32 Biasing the MOSFET using a large drain-to-gate feedback resistance, RG.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 56
 VDD VSS VGS
I D1 I REF
R

I D2
1
mn Cox W VGS Vt 2
2 L 2
I D1
1
mn Cox W VGS Vt 2 W / L 2
2 L 1 I D 2 I REF
W / L 1
Figure 4.33 (a) Biasing the MOSFET using a constant-current source I. (b) Implementation of the constant-current source I
using a current mirror.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 57
 saturasi vD vG Vt
VDD vD
k n vGS Vt
1 'W
iD iD
2

RD 2 L
1 W
iD k n' VGS vgs Vt 2
2 L
vGS VGS vgs 1 W
k n' VGS Vt 2 kn' W VGS Vt vgs 1 kn' W vgs 2
2 L L 2 L
Untuk 1 k ' W v 2 k ' W V V v
n gs n GS t gs
2 L L
atau v 2V V
gs GS t

atau vgs 2VOV

iD I D k n'
W
VGS Vt vgs
L
Untuk sinyal kecil iD I D id sehingga id k n' W VGS Vt v gs dapat ditulis id g m v gs
L
dengan g m k n'
W
VGS Vt atau g m k n'
W
VOV
L L
Figure 4.34 Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier.

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 iD
1
mn Cox W vGS Vt 2
2 L
W
g m k n' VGS Vt
L
1 'W i
ID
2
k n VOV gm D
2 L vGS v V
GS GS

Figure 4.35 Small-signal operation of the enhancement MOSFET amplifier.

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 vD vDD RDiD
iD I D id
vD vDD RD I D id

vD vDD RD I D RDid

vD VD RDid

Untuk sinyal kecil vD VD vd

vd RDid g m vgs RD

Penguatan tegangan
vd
Av g m RD
vgs

Figure 4.36 Total instantaneous voltages vGS and vD for the circuit in Fig. 4.34.

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 iD
gm 1
vGS iD
vGS VGS ro
vDS vGS tetap
g m k n'
W
VGS Vt g m k n' W VOV
L L 1
ro
ID
k n VGS Vt I D k n' VOV
1 'W 1 W
ID
2 2

2 L 2 L
VA
ro
W ID
g m 2kn' ID
L
Penguatan tegangan Penguatan tegangan
Av g m RD gm
2I D 2I
D Av g m RD // ro
VGS Vt VOV

Figure 4.37 Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in saturation (the channel-length
modulation effect); and (b) including the effect of channel-length modulation, modeled by output resistance ro = |VA| /ID.

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 61
 Kapasitor kopling untuk memisahkan tegangan DC kn(W/L)=0,25mA/V2 Vt=1,5V VA=50V
dvC
iC 1 Menentukan titik kerja
dt
arus drain untuk MOSFET saturasi

k n VGS Vt 0,25VGS 1,5

1 'W 1
ID
2 2

2 L 2
tegangan drain
VD VDD RD I D 15 10I D
hubungan tegangan drain dan gate
VGS VDS VG VD
sehingga
I D 0,12515 10 I D 1,5
2

Langkah analisis dan dapat diperoleh

1. Tentukan titik kerja DC (quotient)
2. Hitung parameter model ekivalen I D 1,06mA VD 4,4V
rangkaian sinyal kecil
3. Susun rangkaian ekivalen sinyal
kecil
4. Lakukan analisis rangkaian
Figure 4.38 Example 4.10: (a) amplifier circuit; (b) equivalent-circuit model.

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 kn(W/L)=0,25mA/V2 Vt=1,5V VA=50V

I D 1,06mA VD 4,4V

2 Menghitung parameter model rangkaian ekivalen

W
g m k n' VGS Vt
L
g m 0,254,4 1.5 0,725mA / V

VA
ro
ID
Langkah analisis 50
1. Tentukan titik kerja DC (quotient) ro 47k
2. Hitung parameter model ekivalen 1,06m
rangkaian sinyal kecil
3. Susun rangkaian ekivalen sinyal
kecil
4. Lakukan analisis rangkaian

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 63
 kn(W/L)=0,25mA/V2 Vt=1,5V VA=50V

I D 1,06mA VD 4,4V

g m 0,725mA / V ro 47k

3 Menyusun rangkaian ekivalen sinyal kecil

Sumber tegangan DC menjadi hubung singkat
Kapasitor (tak hingga!) menjadi hubung singkat

Langkah analisis
1. Tentukan titik kerja DC (quotient)
2. Hitung parameter model ekivalen
rangkaian sinyal kecil
3. Susun rangkaian ekivalen sinyal
kecil
4. Lakukan analisis rangkaian

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 64
 kn(W/L)=0,25mA/V2 Vt=1,5V VA=50V

I D 1,06mA VD 4,4V
4 Melakukan analisis rangkaian
ro 47k tegangan output dengan pengaruh RG
g m 0,725mA / V
diabaikan
vo g m v gs RD // RL // ro
penguatan tegangan
vo g m v gs RD // RL // ro
Av
vi v gs

1
Av 0,725m
1 1 1

10k 10k 47k
Av 3,3V / V

ii
vi vo
vo vi
vi
1 1 3,3 4,3 vi
RG vi RG
RG RG
v vi R 10M
Rin i G 2,33M
ii 4,33 iv 4,33 4,33
RG
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 65
 Figure 4.39 Development of the T equivalent-circuit model for the MOSFET. For simplicity, ro has been omitted but can
be added between D and S in the T model of (d).

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 Model T MOSFET

Figure 4.40 (a) The T model of the MOSFET augmented with the drain-to-source resistance ro. (b) An alternative
representation of the T model.

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 Figure 4.41 Small-signal equivalent-circuit model of a MOSFET in which the source is not connected to the body.

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 Table 4.2

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 Rangkaian dasar (DC) penguat
dengan MOSFET

Figure 4.42 Basic structure of the circuit used to realize single-stage discrete-circuit MOS amplifier configurations.

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 Figure E4.30

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 Definisi model makro penguat

Penguatan tegangan v Penguatan tegangan vo

Avo o keseluruhan beban Gvo
beban terbuka vi vsig
RL RL
terbuka
vo vo
Penguatan tegangan Av Penguatan tegangan Gv
vi vsig
keseluruhan
Penguatan arus io
A
beban hubung singkat is i
i RL 0

io
Penguatan arus Ai
ii

Table 4.3

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 Definisi model makro penguat

Resistansi input v Resistansi output vx

Ri i Ro
tanpa beban ii riil ix vi 0
RL

vi
Resistansi input Rin
ii

vx
Resistansi output Rout
ix vsig 0
Transkonduktansi io
Gm
hubung singkat vi RL 0

Table 4.3

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 Definisi model makro penguat

vi Rin

vsig Rin Rsig
RL
Av Avo
RL Ro
Avo Gm Ro
Rin RL
Gv Avo
Rin Rsig RL Ro
Ri
Gvo Avo
Ri Rsig
RL
Gv Gvo
RL Ro
Table 4.3

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 Figure 4.43 (a) Common-source amplifier based on the circuit of Fig. 4.42. (b) Equivalent circuit of the amplifier for
small-signal analysis. (c) Small-signal analysis performed directly on the amplifier circuit with the MOSFET model
implicitly utilized.

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 Figure 4.44 (a) Common-source amplifier with a resistance RS in the source lead. (b) Small-signal equivalent circuit with
ro neglected.

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 Figure 4.45 (a) A common-gate amplifier based on the circuit of Fig. 4.42. (b) A small-signal equivalent circuit of the
amplifier in (a). (c) The common-gate amplifier fed with a current-signal input.

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 Figure 4.46 (a) A common-drain or source-follower amplifier. (b) Small-signal equivalent-circuit model. (c) Small-signal
analysis performed directly on the circuit. (d) Circuit for determining the output resistance Rout of the source follower.

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 Table 4.4

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 Table 4.4 (Continued)

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 Figure 4.47 (a) High-frequency equivalent circuit model for the MOSFET. (b) The equivalent circuit for the case in which
the source is connected to the substrate (body). (c) The equivalent circuit model of (b) with Cdb neglected (to simplify
analysis).

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 Figure 4.48 Determining the short-circuit current gain Io /Ii.

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 Table 4.5

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 Figure 4.49 (a) Capacitively coupled common-source amplifier. (b) A sketch of the frequency response of the amplifier
in (a) delineating the three frequency bands of interest.

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 Figure 4.50 Determining the high-frequency response of the CS amplifier: (a) equivalent circuit; (b) the circuit of (a)
simplified at the input and the output;

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 Figure 4.50 (Continued) (c) the equivalent circuit with Cgd replaced at the input side with the equivalent capacitance Ceq;
(d) the frequency response plot, which is that of a low-pass single-time-constant circuit.

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 Figure 4.51 Analysis of the CS amplifier to determine its low-frequency transfer function. For simplicity, ro is neglected.

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 Figure 4.52 Sketch of the low-frequency magnitude response of a CS amplifier for which the three break frequencies are
sufficiently separated for their effects to appear distinct.

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 Figure 4.53 The CMOS inverter.

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 Figure 4.54 Operation of the CMOS inverter when vI is high: (a) circuit with vI = VDD (logic-1 level, or VOH); (b)
graphical construction to determine the operating point; (c) equivalent circuit.

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 Figure 4.55 Operation of the CMOS inverter when vI is low: (a) circuit with vI = 0 V (logic-0 level, or VOL); (b) graphical
construction to determine the operating point; (c) equivalent circuit.

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 Figure 4.56 The voltage transfer characteristic of the CMOS inverter.

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 Figure 4.57 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms;
(c) trajectory of the operating point as the input goes high and C discharges through QN; (d) equivalent circuit during the
capacitor discharge.

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 Figure 4.58 The current in the CMOS inverter versus the input voltage.

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 Figure 4.59 (a) Circuit symbol for the n-channel depletion-type MOSFET. (b) Simplified circuit symbol applicable for the
case the substrate (B) is connected to the source (S).

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 Figure 4.60 The current-voltage characteristics of a depletion-type n-channel MOSFET for which Vt = 4 V and kn(W/L)
= 2 mA/V2: (a) transistor with current and voltage polarities indicated; (b) the iDvDS characteristics; (c) the iDvGS
characteristic in saturation.

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 Figure 4.61 The relative levels of terminal voltages of a depletion-type NMOS transistor for operation in the triode and the
saturation regions. The case shown is for operation in the enhancement mode (vGS is positive).

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 Figure 4.62 Sketches of the iDvGS characteristics for MOSFETs of enhancement and depletion types, of both polarities
(operating in saturation). Note that the characteristic curves intersect the vGS axis at Vt. Also note that for generality
somewhat different values of |Vt| are shown for n-channel and p-channel devices.

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 Figure E4.51

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 Figure E4.52

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 Figure 4.63 Capture schematic of the CS amplifier in Example 4.14.

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 Figure 4.64 Frequency response of the CS amplifier in Example 4.14 with CS = 10 mF and CS = 0 (i.e., CS removed).

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 Figure P4.18

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 Figure P4.33

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 Figure P4.36

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 Figure P4.37

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 Figure P4.38

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 Figure P4.41

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 Figure P4.42

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 Figure P4.43

Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 110
 Figure P4.44

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 Figure P4.45

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 Figure P4.46

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 Figure P4.47

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 Figure P4.48

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 Figure P4.54

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 Figure P4.61

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 Figure P4.66

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 Figure P4.74

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 Figure P4.75

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 Figure P4.77

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 Figure P4.86

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 Figure P4.87

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 Figure P4.88

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 Figure P4.97

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 Figure P4.99

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 Figure P4.101

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 Figure P4.104

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 Figure P4.117

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 Figure P4.120

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 Figure P4.121

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 Figure P4.123

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