Anda di halaman 1dari 21

ECE-E434 Digital Electronics

Lectures 15: SRAM (Read Operation); Aux.


Circuits; SRAM (Write Operation); DRAM

Instructor: Pouya Dianat


Nov 14 2017
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Static RAM (SRAM) as memory cell


ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

SRAM: Read Operation


ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

SRAM: Read Operation


• Bit lines are pre-charged to VDD
• Read operation has to be non-
destructive:

• Therefore:
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

SRAM: Read Operation Design Criteria


ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

SRAM: Speed of Read Operation


ECE-E434
Digital Electronics
Memory Circuits– Ch. 16
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Auxiliary Circuits for RAMs


• For read operation in SRAM, a pre-
charging circuit and a sense amplifier
are required.
• These circuits use differential
input/outputs: That is their operation
requires both H and L bit lines.
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Pre-charge and Equalization Circuits


1. In a read operation, fp, is activated for pre-charging;
2. Q8 and Q9 will conduct to connect (both) B and B lines to VDD/2;
3. fp is deactivated and bit lines are floated, prior to word line activation.
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Sense Amplifier
1. Word line is activated; The desired cell is activated;
2. During the read operation the voltage of the lines changes by small value of DV;
3. fs is activated; Q6 and Q5 connect the sense amplifier (latch) to VDD and GND;
4. The positive feedback loop in the SA (latch) pushes the voltages of bit lines to the
desired value.
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Operation of the Sense Amplifier

Transconductance of QN
Calculated at VDD/2

Transconductance of QN
Calculated at VDD/2
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

SRAM: Write Operation


• Assuming that the cell is storing a logic 1 before the write operation; that is:

• We want to write a 0 to the cell; that is the bit line B=0;


• Note there is no pre-charging for the write operation; What was pre-
charging, anyway?!
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

SRAM: Write Operation


• For the FF to toggle, Q1-Q5 can not
provide enough current (remember
why?)
• Q4-Q6 should be designed such that
enough current could be sourced to
toggle Q.
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

SRAM: Write Operation


• W operation is faster than R, because:
• It does not require the discharging of large line capacitance.
• The voltages of B and B are driven to their required VDD and 0V.

• The W operation delay is equal to the time required for regenerating signal to
propagate around the feedback loop. We calculated this for SRFF previously.
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Dynamic RAM
• There may be leakage  Cs loses its voltage.
• Note: Cells need to be refreshed every few milli-seconds.
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Read Operation in DRAM


• Operation is similar to SRAM; although, NO B line
• Cs is generally much much smaller than CB
ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Obtaining Differential Operation in


DRAMs
• A dummy cell is used that is connected to the B line.