CO1

CMOS VLSI Design (15EC3107)

Course Coordinator:

Dr. Hari Kishore Kakarla

Professor @ ECE

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 TECHNOLOGY
INTRODUCTION

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i) Small Scale Integration:- (10-100) transistors => Example: Logic
gates
ii) Medium Scale Integration:- (100-1000) =>
Example: counters
iii) Large Scale Integration:- (1000-20000) =>
Example:8-bit chip
iv) Very Large Scale Integration:- (20000-1000000) => Example:16 &
32 bit up
v) Ultra Large Scale Integration:- (1000000-10000000) => Example:
Special processors, virtual reality machines, smart sensors

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IC Technology

Moore’s Law
Definition: As Gordon Moore(one of the founder of Intel)
predicted in the early 1970s that number of transistors
per chip continued to double every one and half year or
18 months at the same time dimension of the transistor is
dropped down from 25µm in 1960 to 0.18µm in 2000

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Transistors integrated on a chip

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Symbols for n-MOS and P-MOS

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Cont…

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• We have PMOS and NMOS transistors.
• They are Enhancement mode and Depletion mode of operation

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Mask Layout Encoding Styles for Different materials

BLUE

RED

GREEN

DARK YELLOW

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Accumulation

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Depletion Mode

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Inversion
http://www.kenfreed1.com/flash/mosfet1.html

After forming Channel

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Simulation

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Enhancement mode Transistor
In Enhancement mode transistor channel is going to form after
giving a proper gate voltage.

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n-Mos Depletion mode Transistor

• In Depletion mode transistor channel will be present by the

implant. It can be removed by giving a proper negative gate voltage.

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 Action of Enhancement Mode Transistor
non-saturation Region or linear region : the drain current(Ids) increases
linearly with Vds and the channel starts to narrow on drain side.

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 Cont..
Saturation Region: the drain current remains almost constant. (As the drain
voltage is increased further beyond (Vgs-Vt) the pinch off point starts to move
from the drain end to the source end)

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n-Mos Fabrication (Preparation of Silicon Die)

Steps 1-3

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Cont..
Steps 4-5

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Cont..

Steps 6-9

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Diffusion Process

Diffusion

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n-MOS fabrication process

1) Process is carried out on a thin wafer (75 to 150 mm

dia, .4mm thick)

• Doped with boron impurity concentration of

1015/cm3 to make substrate

Substrate

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n-MOS fabrication process

2) A layer of SiO2 grown all over the surface (1µm thick) to

protect.

SiO2

Substrate

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Cont….

3) Then the oxidized wafer is covered with Photo resist.

Photo-Resist
SiO2

Substrate

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Cont…

4) Now the wafer is exposed to UV Light through a

photo mask to define regions.

Photo-Mask

Photo-Resist
SiO2

Substrate

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Cont….

5.1) Now oxide which is unprotected from photoresist is

etched away.

SiO2

Substrate

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Cont…

5.2) The rest of the photo resist is removed.

Then the further fabrication process is carried out,
say doping.

SiO2 SiO2

Substrate

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 Polysilicon on thin oxide
Thin layer of SiO2(0.1µm) grown and then polysilicon is
deposited on top to form gate structure.

6) Polysilicon layer consists of heavily doped

polysilicon deposited by Chemical Vapor
Deposition (CVD)

SiO2
Poly Si
Thinox

Substrate

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 Metallization

7) Use mask to remove exposed area into which n-type

impurities(phosphorus) are to be diffused to form
source and drain.

SiO2 Poly Si
Thinox
n n

Substrate

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Cont…..

8) Again thinox is grown all over the surface and is then

masked to expose selected areas of gate, drain and
source to make Contact holes (cut)

SiO2
Poly Si
Thinox
n n

Substrate

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Cont…

9) Finally, whole chip is metal deposited over its surface

for required interconnection pattern.

SiO2
Poly Si
Thinox
n n

Substrate

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• When we need to fabricate both nMOS
and pMOS transistors on the same
substrate we need to follow different
processes.
• The three different processes are , P-
well process ,N-well process and Twin
tub process.

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CMOS P-well Fabrication

Steps 1-4

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Cont..

CMOS P-well inverter showing VDD and VSS Substrate connections

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Substrate and Well taps or Contacts:

The substrate must be tied to a lower potential

to avoid forward biasing the p-n junction
between the p-substrate and n+ NMOS source
or drain.
Similarly, N-well must be tied to a high potential.
This is generally done by adding heavily doped
substrate and well contacts or taps to connect
VDD and VSS, to the substrate and P-well
respectively as shown in the above figure.

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 Formation of n-well regions

Define nMOS and pMOS active areas

Field and Gate Oxidations (thinox)

Form and Pattern Polysilicon

p+ diffusion

n+ diffusion

Contact cuts

Deposit and pattern metallization

Over glass with cuts for bonding pads

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Summary of P-well Process
Mask sequence
 Mask 1: Defines the areas in which the deep p-well diffusion takes place.

 Mask 2: Defines the thin oxide region (where the thick oxide is to be removed or
stripped and thin oxide grown)

 Mask 3: It’s used to pattern the polysilicon layer which is deposited after thin
oxide.
 Mask 4: A p+ mask (anded with mask 2) to define areas where
p-diffusion is to take place.
 Mask 5: We are using the –ve form of mask 4 (p- mask) It
defines where n-diffusion is to take place.
Mask 6: Contact cuts are defined using this mask.
Mask 7: The metal layer pattern is defined by this mask.
Mask 8: An overall passivation (over glass) is now applied and it also defines
openings for accessing pads.

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 Twin-tub Process
It is made with both n-well and p-well region.
Epitaxial layer: High purity silicon grown with accurately
determined dopant concentrations

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Bi-CMOS Technology

Driving capability of MOS transistors is less

Bi-CMOS technology capable to drive large capacitive loads.

The npn transistor is formed an n-well and the additional

p+ base region is located in the well to form the p-base region
of the transistor. The second additional layer, the buried n+
sub collector (BCCD) is added to reduce the n-well (collector)
resistance & thus improve the quality of the bipolar transistor.

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Comparison between CMOS and Bipolar technologies
CMOS
• Low static power dissipation
• High input impedance
• High noise margin
• High packing density
• High delay sensitivity to load
• Low output drive current
• Low gm
• Bidirectional capability
• A near ideal switching
device
• Scalable threshold voltage
Bipolar Technologies
• High power dissipation
• Low input impedance
• Low voltage swing logic
• Low packing density
• Low delay sensitivity to load
• High output drive current
• High gm
• Essentially unidirectional
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Cross Sectional View
Bi-CMOS (n-p-n Transistor (orbit 2um CMOS)

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