SAP-1
Block Diagram
SAP1 Architecture
Simple-As-Possible.
One output device with 8 LEDs
16 bytes of RAM
5 instructions
3 with 1 operand,
2 with implicit operands.
Accumulator Architecture
Accumulator, Out Register,
B Register, Memory Address Register (MAR)
Instruction Register (IR).
CON CP EP LM CE L1 E1 LA E A SU EU LB LO
CON CP EP L M CE L I E I L A EA SU EU L B LO
= 1 0 1 1 1 1 1 0 0 0 1 1
= B E 3
CON CP EP L M CE L I E I L A EA SU EU L B LO
= 0 0 1 0 0 1 1 0 0 0 1 1
= 2 6 3
The next three states (T4, T5, and T6) are the execution
cycle of SAP-1.
The register transfers during the execution cycle
depend on the particular instruction being executed.
For instance. LDA 9H requires different register
transfers than ADD BH.
What follows are the control routines for different
SAP-1 instructions.
SAP-1
Simulation
0000 1000
of Program
1111
0001 1111
0000
1110 1001
0101
1010
0011
LDA 9H
ADD AH 1010
1001
OUT
0000
0001
1110
1111
HLT
08
Computer
Halted January 31, 2018
Wednesday,
54
Acknowledgement:
Engr. Rashid Farid Chishti
Lecturer, Faculty of Engineering &
Technology
International Islamic university
Islamabad.
Mobile: 0321 5300 497
E-mail: chishti@iiu.edu.pk