ARM Processor

ARM Basic
Von-Neumann and Hardward Architecture
 Computer Performance
1. It is totally based on the CPU time
2. Cpu time is depend on how much time cpu need to execute a program.
3. It is totally depend on total number of cycles , instruction and program
also.
CPU Time = Time / Program
Time / program =
(Time / Cycle)*(Cycle/Instruction)*(Instruction/Program)
 What Is ARM?

• Advanced RISC Machine

• First RISC microprocessor

for commercial use

• Market-leader for low-power

and cost-sensitive embedded
applications
 Features

• Architectural simplicity
which allows
• Very small implementations
which result in
• Very low power consumption
 The History of ARM

• Developed at Acorn Computers

Limited,
of Cambridge, England,
between 1983 and 1985
• Problems with CISC:
• Slower then memory parts
• Clock cycles per instruction
 ARM Architecture

• Typical RISC architecture:

• Large uniform register file
• Load/store architecture
• Simple addressing modes
• Uniform and fixed-length instruction fields
 ARM Architecture (2)

• Enhancements:
• Each instruction controls the ALU and
shifter
• Auto-increment
and auto-decrement addressing modes
• Multiple Load/Store
• Conditional execution
 ARM Architecture (3)

• Results:
• High performance
• Low code size
• Low power consumption
• Low silicon area
 Pipeline Organization

• Increases speed –
most instructions executed in single
cycle
• Versions:
– 3-stage (ARM7TDMI and earlier)
– 5-stage (ARMS, ARM9TDMI)
– 6-stage (ARM10TDMI)
ARM Pipeline Execution
 Pipeline Organization (3)
• 5-stage pipeline: • Stages:
– Reduces work per cycle =>
allows higher clock frequency Fetch
– Separates data and Decode
instruction memory =>
reduction of CPI Execute
(average number
of clock Cycles Per Instruction) Buffer/data

Write-back
•
The Registers
ARM has 37 registers all of which are 32-bits long.

– 1 dedicated program counter

– 1 dedicated current program status register
– 5 dedicated saved program status registers
– 30 general purpose registers
• The current processor mode governs which of several banks is accessible. Each mode can access

– a particular set of r0-r12 registers

– a particular r13 (the stack pointer, sp) and r14 (the link
register)
– the program counter, r15 (pc)
– the current program status register, cpsr
Privileged modes (except System) can also access

– a particular spsr (saved program status register)

 DIFFERENT STATES
• When the processor is executing in ARM state:

– All instructions are 32 bits wide

– All instructions must be word aligned

• When the processor is executing in Thumb state:

– All instructions are 16 bits wide

– All instructions must be halfword aligned

• When the processor is executing in Jazelle state:

– All instructions are 8 bits wide

– Processor performs a word access to read 4
instructions at once
Data Sizes and Instruction
Sets
• The ARM is a 32-bit architecture.

• When used in relation to the ARM:

– Byte means 8 bits
– Halfword means 16 bits (two bytes)
– Word means 32 bits (four bytes)

• Most ARM’s implement two instruction sets

– 32-bit ARM Instruction Set
– 16-bit Thumb Instruction Set

• Jazelle cores can also execute Java bytecode

 Processor Mode

1. Supervisor Mode
2. Fast Interrupt Request:
3. Interrupt Request
4. Abort
5. Undefined
6. System
7. User
 Operating Modes
• Seven operating modes:
– User
– Privileged:
• System (version 4 and above)
• FIQ
• IRQ
• Abort exception modes
• Undefined
• Supervisor

18
 Operating Modes (2)
Exception modes:
User mode: – Entered
upon exception
– Normal program
execution mode – Full access
to system resources
– System resources
unavailable – Mode changed freely
– Mode changed
by exception only
 Exceptions
Exception Mode Priority IV Address
Reset Supervisor 1 0x00000000
Undefined instruction Undefined 6 0x00000004
Software interrupt Supervisor 6 0x00000008
Prefetch Abort Abort 5 0x0000000C
Data Abort Abort 2 0x00000010
Interrupt IRQ 4 0x00000018
Fast interrupt FIQ 3 0x0000001C

Table 1 - Exception types, sorted by Interrupt Vector addresses

20
 ARM Registers

• 31 general-purpose 32-bit registers

• 16 visible, R0 – R15
• Others speed up the exception
process
 ARM Registers (2)

• Special roles:
– Hardware
• R14 – Link Register (LR):
optionally holds return address
for branch instructions
• R15 – Program Counter (PC)

– Software
• R13 - Stack Pointer (SP)
 ARM Registers (3)

• Current Program Status Register (CPSR)

• Saved Program Status Register (SPSR)
• On exception, entering mod mode:
– (PC + 4)  LR
– CPSR  SPSR_mod
– PC  IV address
– R13, R14 replaced by R13_mod, R14_mod
– In case of FIQ mode R7 – R12 also replaced
 ARM Registers (4)
System & User FIQ Supervisor Abort IRQ Undefined
R0 R0 R0 R0 R0 R0
R1 R1 R1 R1 R1 R1
R2 R2 R2 R2 R2 R2
R3 R3 R3 R3 R3 R3
R4 R4 R4 R4 R4 R4
R5 R5 R5 R5 R5 R5
R6 R6 R6 R6 R6 R6
R7 R7_fiq R7 R7 R7 R7
R8 R8_fiq R8 R8 R8 R8
R9 R9_fiq R9 R9 R9 R9
R10 R10_fiq R10 R10 R10 R10
R11 R11_fiq R11 R11 R11 R11
R12 R12_fiq R12 R12 R12 R12
R13 R13_fiq R13_svc R13_abt R13_irq R13_und
R14 R14_fiq R14_svc R14_abt R14_irq R14_und
R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC)
CPSR CPSR CPSR CPSR CPSR CPSR
SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und 24
• Processor Modes
The ARM has seven basic operating modes:

– User : unprivileged mode under which most tasks run

– FIQ : entered when a high priority (fast) interrupt is raised

– IRQ : entered when a low priority (normal) interrupt is raised

– Supervisor : entered on reset and when a Software Interrupt

instruction is executed
– Abort : used to handle memory access violations

– Undef : used to handle undefined instructions

– System : privileged mode using the same registers as user mode

 The ARM Register Set
Current Visible
Current Visible Registers
Registers
r0
Abort
SVC
Undef
FIQ
User Mode
Mode
Mode
IRQMode
Mode
Mode
r1
r2
r3 Banked
Banked
Bankedout
out
outRegisters
Registers
Registers
r4
r5
r6 User FIQ IRQ SVC Undef Abort
r7
r8 r8 r8
r9 r9 r9
r10 r10 r10
r11 r11 r11
r12 r12 r12
r13 (sp)
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr
spsr spsr spsr spsr spsr spsr
 Exception Handling
• When an exception occurs, the ARM:
– Copies CPSR into SPSR_<mode>
– Sets appropriate CPSR bits 0x1C FIQ
• Change to ARM state 0x18 IRQ
• Change to exception mode 0x14 (Reserved)
• Disable interrupts (if appropriate) 0x10 Data Abort
– Stores the return address in LR_<mode> 0x0C Prefetch Abort
0x08 Software Interrupt
– Sets PC to vector address
0x04 Undefined Instruction
• To return, exception handler needs to: 0x00 Reset
– Restore CPSR from SPSR_<mode> Vector Table
– Restore PC from LR_<mode> Vector table can be at
0xFFFF0000 on ARM720T
This can only be done in ARM state. and on ARM9/10 family devices
 Program Status Registers
31 28 27 24 23 16 15 8 7 6 5 4 0

N Z C V Q JU n d e f i n e d I F T mode
f s x c

• Condition code flags • Interrupt Disable bits.

– N = Negative result from ALU – I = 1: Disables the IRQ.
– Z = Zero result from ALU – F = 1: Disables the FIQ.
– C = ALU operation Carried out
– V = ALU operation oVerflowed • T Bit
– Architecture xT only
• Sticky Overflow flag - Q flag – T = 0: Processor in ARM state
– Architecture 5TE/J only – T = 1: Processor in Thumb state
– Indicates if saturation has occurred
• Mode bits
• J bit – Specify the processor mode
– Architecture 5TEJ only
– J = 1: Processor in Jazelle state
 Program Counter (r15)

• When the processor is executing in ARM state:

– All instructions are 32 bits wide
– All instructions must be word aligned
– Therefore the pc value is stored in bits [31:2] with bits
[1:0] undefined (as instruction cannot be halfword or
byte aligned)

• When the processor is executing in Thumb state:

– All instructions are 16 bits wide
– All instructions must be halfword aligned
– Therefore the pc value is stored in bits [31:1] with bit
[0] undefined (as instruction cannot be byte aligned)
 Supervisor Mode
1. Entered on reset and when supervisor call instruction is
executed
2. Supervisor mode is the mode that the processor is in after
reset and is generally the mode that an operating system
kernel operates in.
 Fast Interrupt Request Mode
1. Entered when high priority interrupt is raised
 Interrupt Request Mode
1. Entered when normal priority interrupt is raised
 Abort Mode
1. The processor enters abort mode when there is a failed
attempt to access memory
 Undefined Mode
1. Used to handle undefined instruction.
2. Undefined mode is used when the processor encounters an
instruction that is undefined or not supported by the
implementation.
 Undefined Mode
1. Used to handle undefined instruction.
2. Undefined mode is used when the processor encounters an
instruction that is undefined or not supported by the
implementation.
 System Mode
1. System mode is a special version of user mode that allows full
read-write access to the cpsr.
 User Mode
1. User mode is used for programs and applications
 The ARM Register Set
1. Total 37 register

User mode IRQ FIQ Undef Abort SVC

r0
r1
r2 ARM has 37 registers, all 32-bits long
r3
r4 A subset of these registers is accessible in
r5 each mode
r6 Note: System mode uses the User mode
r7 register set.
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr

Current mode Banked out registers

 SP, PC and LR
1. Stack Pointer: It is a small register that stores the address of
the last program request to CPU. Or It hold address of stack.
2. Program Counter: It contain address of instruction being
executed at the current time. Or It hold address of next
instruction.
3. Link Register: It is use to hold the return address of the
function call.
 Banked out register
1. Not in use register and not generally accessible

2. They coming to use when the processor change its mode

3. Eg. When you switch to IRQ mode , then the subset of the

registers change places and some of the IRQ registers coming

to the user mode

4. Each mode having its own stack space and and different

subset of register.
 Banked out register

5. SPSR is used for holding the snapshot of the current system

state at the moment the exception is taken, that is helpful to return
where we were very easy.
Why FIQ handling is faster than handling
IRQ ?
 Program Status Registers
31 28 27 24 23 19 16 15 10 9 8 7 6 5 4 0

NZCV Q[de] J GE[3:0] EA IF T mode

f s
Condition code flags
N = Negative result from ALU
Z = Zero result from ALU
C = ALU operation carried out
V = ALU operation overflowed
Sticky Overflow flag - Q flag
Indicates if saturation has occurred
SIMD Condition code bits - GE[3:0]
Used by some SIMD instructions
IF THEN status bits - IT[abcde]
Controls conditional execution of Thumb
instructions
x c
T bit
T = 0: Processor in ARM state
T = 1: Processor in Thumb state
J bit
J = 1: Processor in Jazelle state
Mode bits
Specify the processor mode
Interrupt Disable bits
I = 1: Disables IRQ
F = 1: Disables FIQ
E bit
E = 0: Data load/store is little endian
E = 1: Data load/store is big endian
A bit
A = 1: Disable imprecise data aborts
Thanks