iCoMET
IBA Sukkur, Pakistan
March 3, 2018
Outline
Introduction
Problem Statement
Proposed Methodology
Demo
Conclusion
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Introduction
design effort.
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Introduction
Traditional Simulation
Manual testbenches take a lot of time.
Manual selection of test vectors results in biased testing
Manual testing can end up erroneous testing setups
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More problems with traditional simulation
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Solution to Biased Testing Problem
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Solution to other problems
Randomized Testbench
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Contribution of the Paper
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Methodology
.v
Automatic
Automatic
Assertion
Generator .gmvh
SystemVerilog Assertions
SVA Simulator/FV
Report
Assertion Failure Report
Report
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NESCOM Project Generation 9
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Testbench Generation
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Automatic Testbench Generator: VerTGen
Clock Period
Clock/
# of Vectors
Reset/Enable
Clock Hold
Event Generator
Value
Testbench
for input Verilog file
.v
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Simulation Data Generation
ModelSim
. v VerTGen Student .vcd
Version
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Assertion Generation Engine
. v
GoldMine .gmv
.vcd
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Assertion Testing
SVA Simulator
IFV
. v
Verifier .report
.gmv
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DEMO
DEMO
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Demo Example
Two blocks A,B exchange data via a common bus :
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Input Verilog file Testbench file
`timescale 1ns/1ps
module arb2(clk, rst, req1, req2, gnt1,
gnt2); module arb2_bench;
reg req2;
input clk, rst; reg req1;
input req1, req2; reg rst;
output gnt1, gnt2; reg clk;
wire gnt2;
reg state; wire gnt1;
reg gnt1, gnt2;
arb2 arb2_ ( .req2(req2),
.req1(req1),
always @ (posedge clk, posedge rst) .rst(rst),
if (rst) .clk(clk),
.gnt2(gnt2),
state <= 0; .gnt1(gnt1));
else initial begin
state <= gnt1; VerTGen $dumpfile("arb2.vcd
$dumpvars(0, arb2_bench.arb2_);
clk = 0;
always @ (*) rst = 1;
if (state) #26 rst = 0;
#500000 $finish;
begin end
gnt1 = req1 & ~req2;
gnt2 = req2; always begin
#25 clk = ~clk;
end end
else
begin always begin
#24;
gnt1 = req1; req2 = $random;
gnt2 = req2 & ~req1; req1 = $random;
end #26;
end
endmodule
endmodule
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Step 2: Initial Simulation (*.VCD FILE)
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Step 3: ASSERTION GENERATION
To run the goldmine in this setup, we need the following two files:
1. Verilog module file
--->keep in the /<GoldMine Directory>/Verilog/<Module Name>/<Module Name>.v
2. Verilog module's Simulation Data (in <Module Name>.vcd format)
---> keep in the /<GoldMine Directory>/goldmine.out/<Module Name>/<Module Name>.vcd
Now, run following command in the terminal in goldmine directory:
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Output file: Assertions
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Conclusion
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Slide 1
Thanks!
http://save.seecs.nust.edu.pk/projects/VerTGen/