ENTITY inv IS
PORT(
i1: IN BIT;
o1: OUT BIT );
END inv;
ARCHITECTURE OF THE
INVERTER
ARCHITECTURE single_delay OF inv IS
BEGIN
o1 <= not (i1) after 5ns;
END single_delay;
DESIGN OF A SIMPLE 2 INPUT
AND GATE WITH A DELAY
ENTITY and2 IS
PORT(
i1, i2 :IN BIT;
o1: OUT BIT);
END and2;
ARCHITECTURE single_delay OF and2 IS
BEGIN
o1 <= (i1 AND i2) after 8ns;
END single_delay;
DESIGN OF A SIMPLE 2 INPUT
OR GATE WITH A DELAY
ENTITY or2 IS
PORT(
i1, i2 :IN BIT;
o1: OUT BIT);
END or2;
ARCHITECTURE single_delay OF or2 IS
BEGIN
o1 <= (i1 or i2) after 8ns;
END single_delay;
SINGLE AND DUAL 2-1
MULTIPLEXER ENTITY
ENTITY single_mux IS
PORT(
s: IN BIT ; --select input
iA, iB : INT BIT; -- iA is selected if
--s=‘0’ and iB is selected if s= ‘1’
oZ: OUT BIT –output of the mux
);
END single_mux;
SINGLE AND DUAL 2-1
MULTIPLEXER ARCHITECTURE
ARCHITECTURE gate_level OF single_mux IS
COMPONENT c1 PORT (
i1 :IN BIT;
o1: OUT BIT);
END COMPONENT;
COMPONENT c2 PORT (
i1, i2 :IN BIT;
o1: OUT BIT);
END COMPONENT;
SINGLE AND DUAL 2-1
MULTIPLEXER ARCHITECTURE
COMPONENT c3 PORT (
i1, i2 :IN BIT;
o1: OUT BIT);
END COMPONENT;
FOR ALL: c1 USE ENTITY WORK.inv(single_delay);
FOR ALL: c2 USE ENTITY WORK.and2(single_delay);
FOR ALL: c3 USE ENTITY WORK.or2(single_delay);
SIGNAL im1, im2, im3: BIT;
SINGLE AND DUAL 2-1
MULTIPLEXER ARCHITECTURE
BEGIN
g0: c1 PORT MAP (s, im1);
g1: c2 PORT MAP (iA, im1, im2);
g2: c2 PORT MAP (iB, s, im3);
g3: c3 PORT MAP (im2, im3, oZ);
END gate_level;
DUAL 2-1 MULTIPLEXER
ENTITY
ENTITY dual_mux IS
PORT(
s: IN BIT ; --select input
iA, iB : IN BIT _VECTOR(1
DOWNTO 0); -- iA is selected if
--s=‘0’ and iB is selected if s= ‘1’
outZ: OUT BIT _VECTOR(1
DOWNTO 0)--output of the mux
);
END dual_mux;
DUAL 2-1 MULTIPLEXER
ARCHITECTURE
ARCHITECTURE element_level OF dual_mux IS
--we use only one component (the single 2:1 mux)
COMPONENT c1 PORT (s, iA, iB: IN BIT;
oZ : OUT BIT);
END COMPONENT;
FOR ALL : c1 USE ENTITY WORK. single_mux (gate_level);
BEGIN
g0 : c1 PORT MAP(sel, inA(0), inB(0), outZ(0)); --the 1st 2:1 mux is
--wired.
g1 : c1 PORT MAP(sel, inA(1), inB(1), outZ(1)); --the 2nd 2:! Mux is
--wired
END element_level;
BEHAVIORAL MODLEING
ARCHITECTURE behavioral_boolean OF
dual_mux IS
SIGNAL temp: BIT_VECTOR(1 downto 0);
BEGIN
temp <= (sel, sel);
--we assign sel to all the bits of the bus temp
outZ <= ((NOT) temp AND inA) OR (temp AND
inB);
END behavioral_boolean;
PROCESS
clk_proc : process
begin
wait until (clk’event and clk =‘1’);
if (reset = ‘1’) then
current_state <= state0;
else
current_state <= next_state;
end if;
end process clk_proc;
End behavioral;
MEALY FINITE STATE
MACHINE(ASYNCHRONOUSLY)
ENTITY USE WORK.ALL;
ENTITY asynchr_state_test IS
END asynchr_state_test;
ARCHITECTURE io_test OF synchr_state_test IS
BEGIN
COMPONENT c1 PORT (
reset : IN BIT;
clk : IN BIT;
xin : IN BIT;
Zout: IN BIT;
stateout: OUT BIT_VECTOR(1 downto 0);
END COMPONENT;
MEALY FIFNITE STATE
MACHINE(ASYNCHRONOUSLY)
FOR g0 : c1 USE ENTITY WORK. asynchr_state_mach(behavioral);
--we have to declare I/O signals that are used in --the test
SIGNAL reset_test : BIT:=‘0’;
SIGNAL clk_test : BIT:= ‘0’;
SIGNAL xin_test : BIT := ‘0’;
SIGNAL zout_test : BIT;
SIGNAL state_out_test: BIT_VECTOR( 1 downto 0);
BEGIN
clock_process : PROCESS is
BEGIN
clk_test <= NOT(clk_test);
wait for 20 ns;
END PROCESS;
g0 : c1 PORT MAP (reset_test, clk_test, xin_test, zout_test, stateout_test) ;
--apply a rest after 30 ns to go to state 0;
t1: reset_test <=
‘0’
‘1’ after 30ns,
‘0’ after 70 ns;
MEALY FIFNITE STATE
MACHINE(ASYNCHRONOUSLY)
t2 : xin_test <=
‘0’,
‘1’ after 50ns, --stay in state0
‘0’ after 90ns, --goto state1
‘1’ after 130ns, --stay in state1
‘0’ after 170ns, --goto state2
‘1’ after 210ns, --goto state3
‘0’ after 250ns, -stay in state3
‘1’ after 290ns, --goto state0
‘0’ after 330ns, --stay in state0
‘1’ after 370ns, --goto state1
‘0’ after 410ns, --goto state2
‘1’ after 450ns, --goto state3
‘0’ after 490ns; -- stay in state0
END io_test;
MOORE FINITE STATE MACHINE
MOORE FINITE STATE MACHINE
ENTITY(synchr_state_mach) IS
PORT(
reset : IN BIT;
clk: IN BIT;
xin : IN BIT;
zout : OUT BIT_VECTOR( 3 downto 0)
);
END synchr_state_mach;
MOORE FINITE STATE MACHINE
USE WORK.ALL;
ENTITY synchr_state_mach_test IS
END synchr_state_mach_test;
ARCHITECTURE io_test OF synchr_state_mach_test
IS
COMPONENT c1 PORT (
reset : IN BIT;
clk : IN BIT;
xin : IN BIT;
Zout: IN BIT;
stateout: OUT BIT_VECTOR(1 downto 0);
END COMPONENT;
MOORE FINITE STATE MACHINE
1. Transport
• Delay independent of input width
2. Inertial
• Delay while reject small pulses
3. Delta
• Minimum delay
• Δ- delays do not accumulate
MODELING PROPOGATION
DELAY
• Signal must remain constant for at least the
propagation delay or greater than the reject
time to be seen on the output
• Pulse rejection can be less than
propagation - must be explicitly stated and
must be less that inertial delay, e.g.,
entity FIFO_LOGIC is
generic (N:integer := 3);
port(clk, push, pop, init : in std_logic;
add : out std_logic_vector(N-1 downto 0);
full,empty,we,nppush,nopop : buffer std_logic);
end FIFO_LOGIC;
library ieee;
use ieee.std_logic_1164.all;
entity shifter is
port (clk, rst, load : in std_ulogic;
data : in std_ulogic( 0 to 7);
q : out std_ulogic ( 0 to 7) );
end shifter;
architecture behavior of shifter is
begin
process (rst, clk ) is
variable qreg : std_ulogic_vector ( 0 to 7);
begin
if rst = ‘1’ then
qreg := “00000000”;
BARREL SHIFTER : BEHAVIORAL