Presented by:-

P.Pushpak kumar (15K95A0434)

S.Manipal Reddy (15K95A0435)
T.Shekhar Goud (15K95A0439)
Under the guidance of
CH. DIVYA
(Asst.professor)
 Contents
 Aim and Objectives
 Introduction
 Errors
 Filters
 Block diagram of existing model
 Proposed scheme
 Block diagram
 Language and Tools used
 Advantages & Applications
 Conclusion
 Future scope
Aim and Objectives

1) To detect and correct errors in digital circuit with more

accuracy.
2) Improve efficiency of time.
Introduction

 In this project by use of ECC’s errors are detected and

corrected for filters
 The scheme can be used for parallel filters that have the
same response and process different input signals
 This project also uses a redundant module incase the data in the
actual module gets lost during transmission
 ERRORS
 Errors can be defined as an accidental mistake
occurring in the circuit without any intention.
 There are two types of errors
Hard errors
Soft errors
FILTERS
 Filters are the circuits which pass the desired signal and
eliminates the unwanted signal
 Filters are of two types
ANALOG FILTERS
DIGITAL FILTERS
 In this project digital filters are used.
Digital Filters
A discrete time filter implements the following equation:

Where x[n] is the input signal, y[n] is the output, and h[l]is the
impulse response of the filter.
When the response h[l] is non-zero, only for a finite number of
samples, the filter is known as a FIR FILTER, otherwise the filter is an
infinite impulse response IIR FILTER.
 In data acquisition and processing applications is also common to
filter several signals with the same response.
Existing System

Parallel filters with the same response.

LANGUAGE:
 Verilog

TOOLS USED:
 MODELSIM –The written HDL code is simulated by using
this tool for checking the functionality of code.

 XILINX-ISE – The simulated code is then synthesized on

this tool and hardware is generated by the based on written
code
Proposed scheme:-
 The filters used in this project are digital FIR filters and
operates on FFT.

 The technique is based on the use of the ECCs. A simple ECC

takes a block of k bits and produces a block of n bits by adding
n−k parity check bits. The parity check bits are XOR
combinations of the k data bits. By properly designing those
combinations it is possible to detect and correct errors.

 The error correction code used is the “Hamming codes”.

BLOCK DIAGRAM OF PROPOSED
MODEL
RTL schematic
TECHNOLOGICAL SCHEMATIC
SIMULATION RESULTS
Advantages:-
 High speed correction
 Low power consumption
 Higher efficiency
Applications:-
Digital signal processing
Communication system
CONCLUSION

 The project has presented a new scheme to protect parallel

filters in signal processing circuits
 The approach is based on applying ECCs to the parallel
filters outputs to detect and correct errors
 The technique provides larger benefits when the number of
parallel filters is large.
FUTURE SCOPE

 ECCs, such as Bose–Chaudhuri–Hocquenghem codes to

correct errors on multiple filters.
 Also this project detects and corrects only single bits, to
correct multiple bits a process called Parseval's check is used.