Low Power VLSI Design: Limits

• Principles of Low Power VLSI Design

– Using the lowest possible supply voltage
– Using the smallest geometry, highest frequency devices but operating them at a
lowest possible frequency
– Using parallelism and pipelining to lower required frequency of operation
– Power management by disconnecting the power source when the system are
idle
– Designing systems to have lowest requirements on subsystems performance for
the given user level functionality.

• Hierarchy of Limits
– Fundamental
– Material
– Device
– Circuit
– Systems
• Two types of limit at each level
– theoretical consideration
– Practical consideration

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 Fundamental Limits

• independent of devices, materials, and circuits

• derived from the basic principles of thermodynamics, quantum mechanics, and electro
magnetics
• The limit from thermodynamic principles results from the need to have, at any node with an
equivalent resistor R to the ground, the signal power P, exceed the available noise power
Pavail

• where 'Y>= 1 is some constant factor

• e-2n is open-circuit mean-square voltage
• B is the bandwidth of the node
– Then at T = 300 K, P, must be larger than 0.104 e V.
• The quantum theoretic limit on low power comes from the Heisenberg uncertainty
principle. In order to be able to measure the effect of a switching transition of duration Δt, it
must involve an energy greater than h / Δt

• where h is the Planck's constant

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• the fundamental limit based on electromagnetic theory results in the velocity of
propagation of a high-speed pulse on an interconnect to be always less than the speed of
light in free space Co,

• where L is the length of the interconnect and T is the interconnect transit time.

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 Material Limits

• Material limits are independent of the particular devices built with the materials and, in
turn, the particular circuits composed from those devices.
• The attributes of a semiconductor material are
– (1) carrier mobility
– (2) carrier saturation velocity
– (3) self-ionizing electric field strength and
– (4) thermal conductivity
Semiconductor material limits that are independent of the structures and the geometry of
devices can be calculated by considering a cube of the undoped material of dimension Δx
that is imbedded in a three-dimensional matrix of similar cubes.
– The voltage difference Vo across a pair of its opposite faces is just as large as necessary to produce an
electric field equal to the self-ionizing electric field strength

– The limit on switching energy and the switching time can then be calculated as the amount of electrostatic
energy stored in the cube and the transit time of a carrier through the cube:

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• The second material level limit arises from heat removal considerations. To derive this
limit, an isolated generic device that resides in an ideal heat sink maintained at temperature
To is considered. The device is hemispherical in shape with a radius of rs = .
• The power or the rate of transfer of the heat energy from the device to the heat sink is then
given by

• An interesting use of the above limit is to compare suitability of GaAs and Si for low-power
applications
• Using representative values, P/td comes out to be 0.21 nS/W for Si and 0.69 ns/W for GaAs

• The interconnect material limit again arises from speed-of-light considerations. The
propagation time through an interconnect of length L of a material with a relative
dielectric constant must satisfy

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 Device Limits

• The device limits are independent of the circuits that may have been composed with
the devices. As the MOSFET device is used significantly more than any other, it will be
considered in this section.

– short-channel effects in bulk MOSFETs can be controlled by using channels with lower impurity
concentration and abrupt retrograde doping profiles.

– MOSFET device leakage current and its overall reliability are affected by factors other than the threshold
voltage shift, for example, bulk punchthrough, gate-induced drain barrier lowering, and impact ionization.

– At the device level, a global interconnect can be modeled as a canonical distributed resistance-capacitance
network. When such a network is driven by an ideal voltage source that applies a unit step function, the
0-90% response time of the network is given by

– The above expression specifies a limit on the minimum response time of an interconnect given its length.

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 Circuit Limits

• The circuit level limits are independent of the architecture of a particular system. There
are four principal circuit level limits
– To be able to distinguish between the "zero" and "one" logic levels with very nearly zero error is the most
basic requirement of a digital logic gate.
– For a static CMOS logic gate this means that at the transition point of the static transfer characteristics of
the gate (i.e., where output voltage is equal to the input voltage), the incremental voltage gain av must
exceed unity in absolute value. A CMOS inverter can only satisfy this requirement if its supply voltage is
larger than a minimum limit Vdd,min

– In practice, a value of Vdd = 0.1 V cannot be used because the threshold voltage would need to be so small
that the drain leakage current in the off state of the MOSFET would be unacceptably large.
– In considering logic and memory circuit behavior, Vdd = 1.0 V appears to be a good compromise for small
dynamic and static power dissipation.

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• The second generic circuit limit for CMOS technology is the often discussed switching
energy per transition

– where Cro is taken as the total load capacitance of a ring oscillator stage, including output diffusion
capacitance, wiring capacitance, and input gate capacitance for an inverter that occupies a substrate area
of 100F2 (F = minimum feature size = 0.1 um).
• The third generic circuit limit is on the intrinsic gate delay and is given by the time taken to
charge/discharge the load capacitance Cro• Hence,

• The fourth generic circuit limit considers a global (i.e., extending from one corner of the
chip to the other) interconnect represented as a distributed resistance-capacitance
network. The response time of this interconnect circuit is

– where Rtr is the output resistance of the driving transistor and Rint and Cint are the total resistance and
capacitance, respectively, of the global interconnect. The circuit should be designed so that Rint < 2.3Rtf to
ensure the delay due to wiring resistance is not excessive.
•

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 System Limits

• System limits depend on all the other limits and are the most restrictive ones in the hierarchy
• There are five generic system limits that are given rise to by
– (1) the architecture of the chip,
– (2) the power-delay product of the CMOS technology used to implement the chip,
– (3) the heat removal capacity of the chip package,
– (4) the clock frequency, and
– (5) its physical size.

• The system switching energy limit is defined by a composite gate that characterizes the
critical path within a macrocell. The critical path is assumed to pass through ncp random
logic gates and include a total interconnect length corresponding to the corner-to-corner
Manhattan distance 2L.
• The system heat removal limit is defined by the requirement that the average power
dissipation of a composite gate P must be less than the cooling capacity of the
packaging.

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 Practical Limits

• The basis for practical limits is the opinion that beyond a certain point in
– scaling,
– the cost of designing,
– manufacturing, testing, and
– packaging will cause the cost per function to level off and begin to increase.
– To facilitate further analysis, the number of transistors per chip N can be expressed as
N = F-2 • D2• PE.
• The optimistic predictions for the minimum feature size F are to reach 0.0625 um by the
second decade of the millennium, for the chip area D to reach over (50 mm)2, and for
the packing efficiency PE to reach one transistor per minimum feature area .
• This would make 100 billion transistor chips economically viable in addition to being
technically possible.

• Quasi-Adiabatic Microelectronics
– In any thermodynamic system that proceeds from one equilibrium process to another, the entropy of a
closed system either remains unchanged or increases.
– During an adiabatic process no loss or gain of heat occurs-consequently the intriguing prospect of inventing
quasi-adiabatic computational technology and reducing the power dissipation to levels beyond the limits of
non adiabatic computation.
– Unlike the unchanging materials and device structures, the circuit configurations used for quasi-adiabatic
operations must change significantly. Without identifying specific circuit configurations and system architectures,
the respective limits cannot be analyzed.

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