G. S. VISWESWARAN
PROFESSOR
ELECTRICAL ENGINEERING DEPARTMENT
INDIAN INSTITUTE OF TECHNOLOGY, DELHI
NEW DELHI 110 016
Email: gswaran@ee.iitd.ac.in
Telephone: (011) 2659 1077; (011) 2685 2525
1
DOMAIN OF CONVERTERS
Sigma Delta
Successive Approx
Subranging/Pipelined
Flash
2
PCM NYQUIST RATE A/D CONVERTERS
3
PCM NYQUIST RATE A/D CONVERTERS
2 2
2
2 1 2V 1 2V
Se N
N
12 12 2 1 12 2
Sx2 Sx2
SNR 10 log 10 log 4.77 6.02N (dB)
S2 V2
e
4
PCM NYQUIST RATE A/D CONVERTERS
8
OVERSAMPLED PCM CONVERTERS
9
OVERSAMPLED PCM CONVERTERS
2 2
Pxy Px (f) Hx (f) and Pey Pe (f) He (f)
S2 Sx2 Sx2
x
SNR 10 log 2 10 log 2 10 log 2 4.77 6.02N 3.02 OSR (dB)
S S 2f f V
ey e B S
11
OVERSAMPLED PCM CONVERTERS
12
NOISE SHAPED OVERSAMPLED
PCM CONVERTERS
13
OVERSAMPLED NOISE SHAPING
14
NOISE SHAPED OVERSAMPLED
PCM CONVERTERS
15
NOISE SHAPED OVERSAMPLED
PCM CONVERTERS
1
1 z 1
Analog Digital
16
FIRST ORDER MODULATION
z 1 z 1
Y(z) 1 1
X(z) E(z)
1z 1z
1
z 1
Y(z) (X(z) Y(z)) E(z)
1z 1
17
FIRST ORDER MODULATION
18
FIRST ORDER MODULATION
19
FIRST ORDER MODULATION
If fB<< fS
1 2 2 f2
Sey (f) 4
fs 12 fs2
fB
Pnoise Sey (f)df
fB
( 2 2 ) 1
Pnoise
36 OSR3
20
Taking OSR to be of the form 2r we can obtain the
SNR as
Sx2 2
SNR 10 log 10 log 9.03r (dB)
S2 3
e
21
FIRST ORDER MODULATION
Noise power coming out of First Order Modulator for an OSR of 128.
22
FIRST ORDER MODULATION
23
SWITCHED CAPACITOR CIRCUITS
DOYEN OF SAMPLED DATA DESIGNS
Sampled Signals:
1 js t
xs (t) x(t) (t kTs ) e
k Ts k
i1 i2
1 T /2 1 T /2 1
i1 i
1 dt dq1 C (V1 V2 )
T 0 T 0 T
25
OTHER REALIZATIONS OF R
26
SWITCHED CAP INTEGRATORS
27
SWITCHED CAP INTEGRATORS
During 1
During 2
Vo (z) (Cs / CF ) z 1 1
H(z) 1
H1 (z) z
V1 (z) (1 z )
28
SWITCHED CAP INTEGRATORS
jT Cs 1 1 1
H(e )
CFT j j RCF
29
SWITCHED CAP INTEGRATORS
31
SWITCHED CAP INTEGRATORS
32
SWITCHED CAP INTEGRATORS
Vo (z) (Cs / CF )
H(z)
V1 (z) (1 z 1 )
34
BACK TO SIGMA DELTA CONVERTERS
35
FINITE OPAMP GAIN
36
FINITE OPAMP GAIN
37
FINITE OPAMP GAIN
1
1
1 A
for CS CF , g ;
2 2
1 1 38
A A
FINITE OPAMP GAIN
gz 1 1 z 1
STF and NTF
1
1 (g )z 1 (g )z 1
39
FINITE OPAMP GAIN
2 f
| NTF |2 | 1 z 1 |2z e j ,
fs
= 1 +2-2 cos
2
For small cos 1
2
Noise power at the output is then
f f
1 B 2 2 1 B 2 2
Pnoise (1 ) df df
fs f 12 fs f 12
B B
1 2 2 2
4 2
1
(1 )
OSR 12 12 3 OSR3
40
FINITE OPAMP GAIN
2
1
1 CS
2 A
(1 ) 1 for 1
2 CF
1
A
2
1
1
A 2
2 A
1
A
1 2 2
4 2
1
Pnoise (1 )2
OSR 12 12 3 OSR3
1 2 1 2 4 2 1
2
OSR 12 A 12 3 OSR3
41
EFFECT OF FINITE BANDWIDTH
CS
Vo CF
Vi 1 CS S CF CS
1 1
C
A CF u F
42
EFFECT OF FINITE BANDWIDTH
CS
Vo CF C
Vo (t) Vi S (1 e ut )
Vi s CF
1
u
43
TIME DOMAIN BEHAVIOUR
2 -0.33 -1
3 1 1
4 0.33 1
5 -0.33 -1
6 1 1
45
TIME DOMAIN BEHAVIOUR (Non Linear)
1 T P N
but Y[T] = Y [0] X V[n 1] V
T i1 T
47
PATTERN NOISE IN MODULATOR
50
PATTERN NOISE IN MODULATOR
Sx2 4
SNR 10 log 10 log 15.05r (dB)
S2 5
e
54
SECOND ORDER MODULATOR
55
INTEGRATOR OVERLOAD
56
INTEGRATOR OVERLOAD
57
INTEGRATOR OVERLOAD
58
INTEGRATOR OVERLOAD
60
INTEGRATOR OVERLOAD
kz 1
[X(z) Y(z)] 1
E(z) Y(z)
1z
kz 1 1 (1k)z 1
X(z) E(z) Y(z)
1z 1 1z 1
X(z)kz 1 E(z)(1 z 1 )
Y(z) 1
1 (1 k)z 1 (1 k)z 1
Clock Output
cycle
2 1
3 1
4 -1
5 1
6 1
7 1
8 -1
61
INTEGRATOR OVERLOAD
62
INTEGRATOR OVERLOAD
63
CIRCUIT NOISE
64
SAMPLING JITTER
dX
X(t ) X(t) .
dt
.2fx .A cos( 2fx t)
65
SAMPLING JITTER
A2
P (2fx)2
2
Since this is assumed to be white, the total error power
in baseband is
2 (2fx)2
P
8 OSR
66
IMPLEMENTATION IMPERFECTIONS
g1 g z 1
2
(X(z) Y(z)) 1
Y 1
E(z) Y(z)
1 1z 1 2z
g1g2z 1
STF
1 (1 a2 g2 g1g2 )z 1 1 ( a2 g2 )z 2
(1 1z 1 )(1 2z 1 )
& NTF
1 (1 a2 g2 g1g2 )z 1 1 ( a2 g2 )z 2
67
IMPLEMENTATION IMPERFECTIONS
68
IMPLEMENTATION IMPERFECTIONS
69
AD Converter
SIGNAL OUTPUTS OF MODULATOR
71
D/A CONVERTER
72
D/A CONVERTER
73
D/A CONVERTER
75