A-Overview of EE3463

Intro to Micro’s – Lab 1

Course Structure
• TA is “Sam” Sreeram Mahadevan
• Understand basic architecture of Micros
• Understand basic Peripheral Functions
• Understand basic issues of embedded design
• Ability to program PIC in Assembly and C
• Ability to program KL25Z in C
Continued
• Will individually make PIC board
• We will use the PIC for the first 7 labs
• Will use Freedom Board with KL25Z
• Will do 2 demonstration labs with KL25Z
• Will do introduction to Assembler for PIC
• Will program PIC also in C++
• Will look at assembler for KL25Z and S12
briefly (no test or lab)
• Will look at programming in C for KL25Z
• Will cover some interfacing
Topic to cover
• Introduction: Programmers model
• PIC
• Build circuit
• Program in ASM
• Program in C
• KL25Z (Freedom Board)
• Program mostly in C
• Hardware and Interfacing issues
• Advanced topics
History of Computers
• Abacus 500 BC
• Adding machine Pascal 1823
• 1940’s Relay memory + Vacuum tubes ENIAC
(1950) Programmed with cables
• Transistors 1948, core memories 1950’s
• Moore’s Law= number of transistors doubles on
chips every 1.5-2 years LSI, VLSI Big Main
frames (I used an IBM 1620 in 1964; 2K)
• 1977 TRS-80,Apple II, Commodore PET
• 1981 IBM PC with Gates MS-DOS
Core Memory Board
Images of early computers
Embedded Processors
• 1960 Apollo guidance computer and
Minuteman II guidance computer
• Caused a quad nand gate to drop from $1000 per
chip to $3!
• 1970’s Automotive industry wanted to use
computers 1978 Cadillac Seville
The chip, a modified 6802, drove the car's "Trip
Computer," a flashy dashboard bauble that
displayed mileage and other trivia. Today that
kind of microprocessor muscle could barely
adjust your mirrors.
What is the difference?
Microprocessors: Intel, AMD,
few others
Microcontrollers:

Freescale MC68HC11, 12, S12

PIC 10,12,16,17,18,24,32,dS
Atmel AVR tiny, mega, XMEGA, 32
Infineon
Intel
Many more
Embedded Processor Manufactures
1 AMCC 20 NEC
2 Altera 21 Panasonic
3 Analog Devices 22 Parallax
4 Atmel 23 NXP Semiconductors
5 Charmed Labs 24 Rabbit Semiconductor
6 Cypress Semiconductor 25 Renesas Electronics
7 Dallas Semiconductor 26 Rockwell
8 ELAN Microelectronics Corp. 27 Silicon Laboratories
9 Energy Micro 28 Silicon Motion
10 EPSON Semiconductor 29 Sony
11 Freescale Semiconductor 30 STMicroelectronics
12 Fujitsu 31 Texas Instruments
13 Holtek 32 Toshiba
14 Infineon 33 Ubicom
15 Intel 34 Xemics
16 Lattice Semiconductor 35 Xilinx
17 Maxim Integrated 36 XMOS
18 Microchip Technology 37 ZiLOG
19 National Semiconductor 38 Others
Micro What ?
• Microprocessor: A VLSI Chip that contains the
central processor and control circuits to move
data in and out of the chip
• Microcomputer: A desk top or lap top computer
that uses a microprocessor and a number of
support chips to provide memory, I/O, Disc
Storage, Displays and input devices for general
purpose applications
• Microcontroller: A chip that has most of the
support on the same chip as the CPU used for
a dedicated application
ARM Cores
Many Manufactures are now using the ARM
cores:
Actions, Qualcomm, Allwinner, HiSilicon, TI,
Apple, Ziilabs, Samsung, Freescale, Nvidia,
STMicroelectronics, Atmel, DEC, Fujitsu,
Toshiba, Altera, Xilinx and over 200 others

Trend is to focus on peripherals and the specific

expertise of the various companies
PIC vs. S12 vs. KL25Z
•High pin count used with SLK board
•16 Bit processor
•Large instruction set >200
•Von Neumann Architecture
•12K RAM
•256K Program Flash (8 bits)
•4K EEPROM
S12 Programmer’s Model
Programmers Model
• A B D registers
• A and B for high and low bytes of the 16 bit D
• Index registers
• Are also used with some of the math instructions as
well as for index addressing
• Program counter
• Works the same as any PC but can be written to
directly
• Stack pointer
• Full SP, Grows downward from top of RAM
• CCR – 5 codes (H,N,Z,V,C) plus stop and int
Groups of Instructions
• Data Transfer and Manipulation
• Arithmetic
• Logic and Bit
• Data Test
• Branch
• Function Call
• Fuzzy Logic
1- Transfer and Manipulation
Table 1.4 Load and store instructions
Load Instructions
Mnemonic Function Operation
ldaa <opr> Load A A ¬ [opr]
ldab <opr> Load B B ¬ [opr]
ldd <opr> Load D A:B ¬ [opr]:[opr+1]
lds <opr> Load SP SP ¬ [opr]:[opr+1]
ldx <opr> Load index register X X ¬ [opr]:[opr+1]
ldy <opr> Load index register Y Y ¬ [opr]:[opr+1]
leas <opr> Load effective address into SP SP ¬ effective address
leax <opr> Load effective address into X X ¬ effective address
leay <opr> Load efective address into Y
Y ¬ effective address
Store Instructions
Mnemonic Function Operation
staa <opr> Store A in a memory location m[opr] ¬ [A]
stab <opr> Store B in a memory location m[opr] ¬ [B]
std <opr> Store D in a memory location m[opr]:m[opr+1] ¬ [A]:[B]
sts <opr> Store SP in a memory location m[opr]:m[opr+1] ¬ [SP]
stx <opr> Store X in a memory location m[opr]:m[opr+1] ¬ [X]
sty <opr> Store Y in a memory location m[opr]:m[opr+1] ¬ [Y]
Transfer and Exchange
- Transfer instructions copy the contents of a CPU register into another CPU
register.
- TFR is the universal transfer instruction, but other mnemonics are accepted
for compatibility with the 68HC11.
- The TAB and TBA instructions affect the N, Z, and V condition code bits.
- The TFR instruction does not affect any condition code bits. For example,
TFR D,X ; [D]  X
TFR A,B ; [A]  B
TFR A,X ; sign-extended of[A]  X ; A is signed extended to 16-bit
and assigned to X
TFR X,A ; X[7:0]  A ; lower 8 bits copied to A
Exchange

-The EXG instruction exchanges the contents of a pair of registers. For example,

exg A, B
exg D,X
exg A,X ; A ¬ X[7:0], X ¬ $00:[A]
exg X,B ; X ¬ $00:[B], B ¬ X[7:0]

-The SEX instruction sign-extend an 8-bit two’s complement number into a 16-bit
number so that it can be used in 16-bit signed operations. For example,

SEX A,X
Move Instructions
Move Instructions
- These instructions move data bytes or words from a source to a destination
in memory.
- Six addressing modes are allowed . For example,

movb $100,$800

movw 0,X, 0,Y

Manipulation
• Rotate (Through Carry Bit)
• Right
• Left
• Logical Shift (Brings in zero)
• Right
• Left
• Arithmetic Shift
• Right (Replicates 7th bit and discards 0th bit)
• Left (Discards 7th bit and brings in a 0)
Arithmetic Instructions
• Add
• ABA, ABX,ABY,ADCA,ADCB,ADDA,ADDB,ADDD
• Sub
• SBA,SBCA,SBCB,SUBA,SUBB,SUBD
• Multiply
• MUL,EMUL,EMULS,EMACS
• Divide
• IDIV,IDIVS,FDIV,EDIV,EDIVS
• Two’s complement
• SEX – sign extend
Logic and Bit Instructions
Table 2.8 Summary of Booleran logic instructions
Mnemonic Function Operation
ANDA <opr> AND A with memory A ¬ (A)  (M)
ANDB <opr> AND B with memory B ¬ (B)  (M)
ANDCC <opr> AND CCR with memory (clear CCR CCR ¬ (CCR) (M)
EORA <opr> bits) A ¬ (A)  (M)
EORB <opr> Exclusive OR A with memroy B¬ (B) (M)
ORAA <opr> Exclusive OR B with memory A ¬ (A) + (M)
ORAB <opr> OR A with memory B ¬ (B) + (M)
ORCC <opr> OR B with memory CCR ¬ (CCR) + (M)
CLC OR CCR with memory C¬0
CLI Clear C bit in CCR I¬0
CLV Clear I bit in CCR V¬0
COM <opr> Clear V bit in CCR M ¬ $FF - (M)
COMA One's complement memory A ¬ $FF - (A)
COMB One's complement A B¬ $FF - (B)
NEG <opr> One's complement B M ¬ $00 - (M)
NEGA Two's complement memory A ¬ $00 - (A)
NEGB Two's complement A B¬ $00 - (B)
Two's complement B
Data Test Instructions
Compare Instructions

- are executed to set the condition flags of the CCR register

- are often used to implement the program loop

CBA compare A to B
CMPA compare A to a memory location or value
CMPB compare B to a memory location or value
CPD compare D to a memory location or value
CPS compare S to a memory location or value
CPX compare X to a memory location or value
CPY compare Y to a memory location or value
TST test a memory location for negative or zero
TSTA test A for negative or zero
TSTB test B for negative or zero
BITA logic AND A with memory
BITB logic AND B with memory
Branch Instructions
JMP– ext or indx Use bits in ccr-HNZVC
BCC BCS
All branch use relative BEQ BNE
(Lxxx for long rel) BGE BGT
BHS BHI
BRA-br always BLE BLT
LBRA-long branch BLS BLO
BRN-never (debug) BMI BPL
BRSET-BRCLR BVS BVC
TBEQ - TBNE IBEQ IBNE
Function Call Instructions
• JSR
• CALL
• RTI, RTC,RTS
• WAI

• Stack operations
• PSHA,PSHB,PSHC,PSHD,PSHX,PSHY
• PULA,PULB,PULC,PULD,PULX,PULY
• SWI
• NOP
Fuzzy Logic Instructions
4 fuzzy logic Other Useful Inst
ETBL TBL
MEM EDIV EDIVS
REV EMACS
REVW EMAX EMAXM
WAV EMIND EMINM
EMUL EMULS
Addressing Modes
1. Inherent
2. Immediate
3. Direct
4. Extended
5. Indexed
6. Relative
Programmer’s model &
Architecture of KL25Z
ARM Core
Freescale Chip
KL25Z128VLK4
• Core:
48 MHz ARM Cortex-M0+ core

• Peripherals:
All Freescale modules
ARM Cortex-M0+ Core up to 48 MHz
• Single-cycle access to I/O: Up to 50 percent faster
than standard I/O, improves reaction time to
external events allowing bit banging and software
protocol emulation
• Two-stage pipeline: Reduced number of cycles per
instruction (CPI), enabling faster branch instruction
and ISR entry, and reducing power consumption
• Excellent code density vs. 8-bit and 16-bit MCUs -
reduces flash size, system cost and power
consumption
• Optimized access to program memory: Accesses
on alternate cycles reduces power consumption
Continued ARM Core
• 100 percent compatible with ARM Cortex-M0 and a
subset ARM Cortex- M3/M4: Reuse existing
compilers and debug tools
• Simplified architecture: 56 instructions and 17
registers enables easy programming and efficient
packaging of 8/16/32-bit data in memory
• Linear 4 GB address space removes the need for
paging/banking, reducing software complexity
• ARM third-party ecosystem support: Software and
tools to help minimize development time/cost
Continue ARM Features
• Micro Trace Buffer: Lightweight trace solution allows
fast bug identification and correction
• BME: Bit manipulation engine reduces code size and
cycles for bit oriented operations to peripheral
registers eliminating traditional methods where the
core would need to perform read-modify-write
operations.
• Up to 4-channel DMA for peripheral and memory
servicing with minimal CPU intervention
• Ultra low-power: Extreme dynamic efficiency: 32-bit
ARM Cortex-M0+ core combined with Freescale 90
nm thin film storage flash
Peripheral Features
• Memories
• 128 KB Flash
• 6 KB SRAM
• System integration
• Power management and mode controllers
• Low-leakage wakeup unit
• Bit manipulation engine for read-modify-write peripherals
• DMA controller
• COP timer
• Clocks
• Clock generation module with FLL and PLL for system and
CPU clock generation
• 4MHz and 32 kHz internal reference clock
• Low-power 1khz RC oscillator for RTC and COP watchdog
Continued
• Analog peripherals
• 16 bit SAR ADC w/ DMA support
• 12 bit DAC w/ DMA support
• High speed comparator
• Comm
• 2 SPI
• USB dual-role controller with built in FS/LS transceiver
• USB voltage regulator
• 2 I2C modules
• 1 low-power Timer
• System tick timer
• Human-Machine Interfaces
• GPIO controller
• Cap touch sense input interface module
General Features
• Timing and Control:
• Powerful timer modules which support general purpose,
PWM, and motor control functions
• Periodic Interrupt Timer for RTOS task scheduler time
base or trigger source for ADC conversion and timer
modules
• System:
• GPIO with pin interrupt functionality
• Wide operating voltage range from 1.71 V to 3.6 V with
flash programmable down to 1.71 V with fully functional
flash and analog peripherals
• Ambient operating temperature ranges from -40 °C to
105 °C
M0+ Functional Blocks

AHB-Lite is a subset of the

full AHB specification and is
intended for use in designs
where only a single bus
master is used. This can
either be a simple single-
master system,
as shown in Figure A-1, or
a multi-layer AHB system
where there is only one
AHB
master per layer

*Advanced Microcontroller Bus Architecture (AMBA)

Programmers Model
R0-R12 R0-R12 are general-purpose registers for data operations.

MSP (R13) The Stack Pointer (SP) is register R13. In Thread mode, the CONTROL
register indicates the stack pointer to use, Main Stack Pointer (MSP) or
Process Stack Pointer (PSP).
PSP (R13)

LR (R14) The Link Register (LR) is register R14. It stores the return information for
subroutines, function calls, and exceptions.

PC (R15) The Program Counter (PC) is register R15. It contains the current program address.

PSR The Program Status Register (PSR) combines:

• Application Program Status Register (APSR).
• Interrupt Program Status Register (IPSR).
• Execution Program Status Register (EPSR).
These registers provide different views of the PSR.

PRIMASK The PRIMASK register prevents activation of all exceptions with configurable
priority.

CONTROL The CONTROL register controls the stack used, and optionally the code privilege level,
when
the processor is in Thread mode.
Processor Core Registers

All Registers are 32 Bits

System Control Register Summary
NVIC* that features:
• Up to 32 external interrupt inputs, each with four levels
of priority.
• Dedicated Non-Maskable Interrupt (NMI) input.
• Support for both level-sensitive and pulse-sensitive
interrupt lines.
• Optional Wake-up Interrupt Controller (WIC), providing
ultra-low power sleep mode support.
• Optional relocation of the vector table.

*Nested Vectored Interrupt Controller

Optional debug support:
• Zero to four hardware breakpoints.
• Zero to two watchpoints.
• Program Counter Sampling Register (PCSR) for non-intrusive code
profiling, if at least one hardware data watchpoint is implemented.
• Single step and vector catch capabilities.
• Support for unlimited software breakpoints using BKPT instruction.
• Non-intrusive access to core peripherals and zero-waitstate system
slaves through a compact bus matrix. A debugger can access these
devices, including memory, even when the processor is running.
• Full access to core registers when the processor is halted.
• Optional, low gate-count CoreSight compliant debug access through a
Debug Access
Bus interfaces:
• Single 32-bit AMBA-3 AHB-Lite system interface
that provides simple integration to all system
peripherals and memory.
• Optional single 32-bit single-cycle I/O port.
• Optional single 32-bit slave port that supports
the DAP.
Single-cycle I/O port
The processor optionally implements a single-cycle I/O
port that provides very high speed access to tightly-
coupled peripherals, such as general-purpose-I/O
(GPIO). The port is accessible both by loads and
stores, from the processor and from the debugger.
You cannot execute code from the I/O port.
Processor Core Features
• The ARMv6-M Thumb® instruction set.
• Optionally, an ARMv6-M compliant 24-bit SysTick timer.
• A 32-bit hardware multiplier.
• Support for either little-endian or byte invariant big-endian
• The ability to have deterministic, fixed-latency, interrupt handling.
• Load/store multiple and multicycle multiply instructions that can be
abandoned and restarted to facilitate rapid interrupt handling.
• Optionally, Unprivileged/Privileged support for improved sys integrity.
• C Application Binary Interface compliant exception model enables the
use of pure C functions as interrupt handlers.
• Low power sleep-mode entry using Wait For Interrupt (WFI), Wait For
Event (WFE) instructions, or the return from interrupt sleep-on-exit
Lab
• Will explore several IDE’s and basic commands
• Can’t do simulation on the s12G128, will use
the old board chip s12DT256
• Good practice with IDE and to learn first
instructions!
• Will begin to make the PIC boards