Laura Gonella
Pjysikalisches Institut Uni Bonn
LDO mode fo the Shunt-LDO regulator
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Outline
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Quiescent current
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Line regulation: introduction
• Definition
– Line regulation = ΔVout/ΔVin
• Specs for an LDO in FE-I4
– Line regulation = 1/20
• Measurement
– Switch on the LDO
– Set a certain Iload
– Change the Vin (i.e. change the Vdrop)
– The slope of Vout=f(Vin) gives the line regulation
– The Vin and Vout shown in the following plots are measured with a
wirebond from the chip pad to a measurement point
• Avoid IR drop on the Vin line from the power supply to the pad
• Avoid IR drop on the Vout line from the pad to the DVM
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Line regulation
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Load regulation: introduction
• Definition
– Load regulation = Rout = ΔVout/ΔIload
• Specs for an LDO in FE-I4
– Load regulation = 33mΩ
• Measurement
– Define a certain Vdrop
– Increase the load from 0 to (max) 0.6A
– Measure the Vout in this range of Iload
– The slope of Vout=f(Iload) gives the load regulation
– The measured value of Rout includes regulator output resistance and on
chip wiring resistance
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Load regulation
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Load regulation
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Temperature effects
Vout = 1.2V; Vin = 1.8V; Iload = 0.05A Vout = 1.2V Vin = 1.8V ; Iload = 0.4A
Reflection effect
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Temperature effects
Iload = 0.5A
Iload = 0.6A Once Iload reaches 0.6A the load switches off
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Measurements in climate chamber
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Comments on Rout value
• As far as checked, there seems to be no problem with the test setup
– IR drop on the Vin lines has been taken into account
– Vout is measured at the pad
– Vref has been checked at the pad to exclude shifts
– No parasitic current paths on the board have been observed
• Measurements were done already on regulators from 3 chips from
different wafers which excludes process variation
– The wire bonding scheme was not optimized on all chips to measure the
Vin and the Vout directly at the pad, however the measurements including
IR drop on the Vin and Vout line compare quite well
• The value of Rout measured could to be due to
– the Ron of the pass transistor
– the gain A of the error amplifier
– the on-chip wiring resistance
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Simulation
• Corners at different T
• Only the load regulation for low load current is affected
• To do: post layout simulation with parasitic extraction
T = 27oC T = 120oC
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Regulator safety: overvoltage
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Safety: short at the output
• If the Vout is shorted the regulator can break
– The current through the regulator increases
– The Vds of the pass transistor is ~Vin
• If Vin > 1.5V the pass transistors breaks due to overvoltage
• If Vin = 1.5V no overvoltage occurs but still the power could be too high and
lead to device failure
• Also this failure mode needs more investigation
– Preliminary: Devices which experienced short at the output show an
increased quiescent current
• This is not a concern for Shunt-LDO operation
• The Iin is fixed at the source and cannot increase
• The Vin follows Vout
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