Unit - 2

DATA-PROCESSING CIRCUITS
 Multiplexers
 Multiplex means many into one.
 A Multiplexer is a circuit with many inputs but
only one output.
 By applying control signals, we can steer any
input to the output. Thus it is called a data
selector and control inputs are termed as
select inputs.

 Block diagram of multiplexer

 Multiplexer types:
2-to-1 (1 select line)
4-to-1 (2 select lines)
Inputs Output
8-to-1 (3 select lines)
16-to-1 (4 select lines) A B Y
0 0 D0
0 1 D1
 4-to-1 Multiplexer truth table: 1 0 D2
1 1 D3

 Logic equation of the circuit:

Y = A’B’.D0 + A’B.D1 + AB’.D2 + A B.D3

Ex: If A=0, B=0

Y=0’0’.D0+0’.0D1+0.0’D2+0.0D3

Y=D0
4-to-1 Multiplexer logic circuit:
8-to-1 Multiplexer
Logic circuit

Truth Table
A B C Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7

Logic equation of the circuit:

Y = A’B’C’.D0 + A’B’C.D1 + A’BC’.D2 +…………..+ ABC’.D6+ABC.D7
16-to-1 Multiplexer A B C D Y
0 0 0 0 D0

 Logic circuit 0 0 0 1 D1
0 0 1 0 D2
0 0 1 1 D3

 Truth Table 0 1 0 0 D4
0 1 0 1 D5
0 1 1 0 D6
0 1 1 1 D7
1 0 0 0 D8
1 0 0 1 D9
1 0 1 0 D10
1 0 1 1 D11
1 1 0 0 D12
1 1 0 1 D13
1 1 1 0 D14
1 1 1 1 D15
 The input bits are labeled D0 to D15. Only one
these is transmitted to the output.

 Which one depends on the value of ABCD, the

control input.

 For instance, when ABCD=0000

Y=D0

 Logic equation of the circuit:

Y = A’B’C’D’.D0 + A’B’C’D.D1 + A’B’CD’.D2 +…..
……..+ ABCD’.D14+ABCD.D15
The 74150
 When 16-to-1 Multiplexer’s OR gate changed to
NOR gate, the effect is, we get the complement
of the selected data bit rather than the data bit
itself.
 For instance, when ABCD=0111, the output is
Y=D’7
 This is the Boolean equation for a typical
transistor-transistor logic (TTL) multiplexer
because it has an inverter on the output that
produces the complement of the selected data
bit.
 The 74150 is a 16-to-1 TTL multiplexer with the
following pin diagram.
 The output Y = Dn’ where n is the decimal
equivalent of ABCD.
Truth table of 74150
Multiplexer Logic A B C D Y
0 0 0 0 1
 Digital design usually 0 0 0 1 0
begins with a truth 0 0 1 0 1
0 0 1 1 1
table.
0 1 0 0 1
 Standard methods for 0 1 0 1 1
implementing a truth 0 1 1 0 0
0 1 1 1 0
table: SOP, POS and
1 0 0 0 1
multiplexer solution. 1 0 0 1 1

 Ex: Use 74150 to 1 0 1 0 1

1 0 1 1 1
implement a below 1 1 0 0 1
given truth table. 1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
Bubbles on Signal lines
 Data sheets often show inversion on some of the
signal lines.
 For instance, bubble on pin 10 – indicates that
output is complement of the selected data bit.
- bubble on the STROBE input (pin 9) –
-Multiplexer is active (enabled) when the
STROBE is low and inactive (disabled) when it is
high.
So the STROBE is called an active-low signal;
it causes something to happen when it is low
rather than when it is high.
Universal Logic Circuit
 Multiplexer sometimes is called universal logic
circuit because 2n-to-1 multiplexer can be used
as a design solution for any n variable truth
table.
 Realization of a 4 variable truth table by 16-to-1
multiplexer.
 This Truth table can be realized using an
8-to-1 multiplexer.
 Procedure adopted here is entered variable

map.
 Realize
Y = F(A,B,C,D)=Σm(0, 2, 3, 4 ,5, 8, 9, 10, 11,
12, 13, 15) using 8-to-1 multiplexer.
Multiplexer
 Nibble Multiplexer:
Demultiplexers
 Demultiplex means one into many.
 A demultiplexer is a logic circuit with one input
and many outputs.

 The 74154 (1-to-16 demultiplexer)

 DeMultiplexer types:
1-to-2 (1 select line)
1-to-4 (2 select lines) – IC 74155
1-to-8 (3 select lines) – IC 74138
1-to-16(4 select lines) – IC 74154

 Select lines determines which output the input

line is connected to.
1-to-4 Demultiplexer
1-to-16 Demultiplexer
The 74154
Pinout diagram Logic diagram
74154 Truth Table
Decoder
 A decoder is a combinational circuit that
connects the binary information from ‘n’ input
lines to a maximum of 2n unique output lines.

2:4 DECODER

 TRUTH TABLE:
INPUT OUTPUT
A B Y0 Y1 Y2 Y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
2:4 DECODER
Boolean Expression

 Y 0 = A’B’
 Y1 = A’B
 Y 2 = AB’
 Y 3 = AB
Decoders
msb
 Decoders are used in many types of applications. One
example is in computers for I/O selection as in previous
slide
 Computer must communicate with a variety of external
devices called peripherals by sending and/or receiving
data through what is known as input/output (I/O) ports

 Each I/O port has a number, called an address, which

uniquely identifies it. When the computer wants to
communicate with a particular device, it issues the
appropriate address code for the I/O port to which that
particular device is connected . The binary port address
is decoded and appropriate decoder output is activated
to enable the I/O port

 Binary data are transferred within the computer on a

data bus, which is a set of parallel lines
 1-OF-16 Decoder
 A decoder is similar to a demultiplexer, with one exception—there
is no data input. The only inputs are the control bits ABCD. This
logic circuit is called 1-of-16 decoder because 1 of the 16 output
line is high.
Using 74154 as Decoder
BCD-to-Decimal Decoder
 BCD is an abbreviation for binary-coded decimal. The BCD code
expresses each digit in a decimal number by its nibble equivalent. To
anyone using BCD code, 0100 0010 1001 is equivalent to 429.

Pinout diagram of 7445

 Example:
 Using a 3-to-8 decoder, design a logic circuit
to realize the following Boolean function
F(A,B,C) = m(2, 3, 5, 6, 7)

 Example:
 Using two 2-to-4 decoders, design a logic
circuit to realize the following Boolean
function
F(A,B,C) =  m(0, 1, 4, 6, 7)
Encoders
 An encoder has
 2N inputs
 N outputs

 An encoder converts an active input signal into a coded

output signal.

 An encoder outputs the binary value of the selected

(or active) input.

 An encoder performs the inverse operation of a

decoder.
 An encoder is a combinational logic circuit that
essentially performs a “reverse” of decoder
functions.
 An encoder accepts an active level on one of its
inputs, representing digit, such as a decimal or
octal digits, and converts it to a coded output
such as BCD or binary.
 Encoders can also be devised to encode various
symbols and alphabetic characters.
 The process of converting from familiar symbols
or numbers to a coded format is called
encoding.
 Decimal-To-BCD Encoder

C
The 74147
Pinout diagram Logic diagram
Exclusive-OR Gates
 The exclusive-OR gate has a high output only when
an odd number of inputs is high.

Y=A B + A B

A B Y
0 0 0
0 1 1
1 0 1
Logic symbol 1 1 0

XOR gate
Truth Table
Parity Generator and Checkers
 Even parity means an n-bit input has an even
numbers of 1s. For instance, 110011.
 Odd parity means an n-bit input has an odd
number of 1s. For instance, 110001.

 Parity Checker:
 Ex-OR gate
Parity Generation

Odd parity generation

 Application
To check data transmission errors
The 74180 – TTL parity generator-checker
Using 74180 to generate odd parity
CLOCKS AND TIMING
CIRCUITS
Clock waveforms
 Static digital logic levels: Voltage levels that
do not change with time.

 Dynamic digital logic levels: Voltage levels

that change with time.

 System Clock: It is the clock signal that

advances the system logic through its
sequences of steps.

 Typical clock wave form used in a digital system.

 Ideal clock waveforms.

 Note: Clock need not to be the perfectly

symmetrical waveform. It could be simply series
of positive (or negative) pulses as shown in
fig(b)

 The main requirement is that the clock be

perfectly periodic, and stable.
 Each signal in the below figure defines a basic
timing interval during which logic operations must
be performed.

 The basic timing interval is defined as the clock

cycle time
 Clock cycle time – It is equal to one period of
the clock wave form.
 Thus all logic elements must complete their
transitions in less than one clock cycle time.
Synchronous Operation
 Nearly all of the circuits in a digital system
(computer) change states in synchronism with the
system clock.
 A change of state will either occur as the clock
transition from low to high or as it transition from
high to low.
 The low to high transition is frequently called the
positive transition (PT). A circuit that changes state
at this time is said to be positive-edge-triggered
 The high to low is called the negative transition
(NT). A circuit that changes state at this time is
said to be negative-edge-triggered.
 Virtually all circuits in a digital system are either
positive-edge-triggered or negative-edge-
triggered, and thus are synchronized with the
system clock.

 There are few exceptions – The operation of

push button (RESET) by a human operator
might result in an instant change of state that is
not in synchronism with the clock. This is called
an asynchronous operation.
Characteristics
 The clock waveform shown above the timeline
is a perfect, ideal clock.
 Characteristics of ideal clock:

1. Clock levels must be absolutely stable.

 Clock is high – level must hold steady value of

+5V (between points a and b)

 Clock is low – level must be unchanging of 0

V. (between points b and c)

 In actual practice, the stability of the clock is

much more important than the absolute value

of the voltage level.
 Ex: Steady, unchanging +4.8V is acceptable
instead of +5.0 V.
2. Time required for the clock levels to change from
high to low or vice versa
- An ideal clock has zero transition time.
- Oscilloscope trace

- Expanded Oscilloscope trace

3. Defines that an ideal clock is its frequency

stability.
The frequency of the clock should be steady and
unchanging over a specified period of time.
Short-term stability: Not to vary much
Long-term stability: deals with longer periods of time.
Propagation Delay Time:
 Propagation delay tp is the time between a
PT (or a NT) at the input of a digital circuit
and the resulting change at the output.

 Propagation delay = tp ≈ tpLH ≈ tpHL

 Pulse-Forming Circuits
 Schmitt Trigger
 A Schmitt trigger is an electronic
circuit that is used to detect whether
a voltage has crossed over a given
reference level.

 It has two stable states and is very

useful as a signal-conditioning
device.

 Given a sinusoidal waveform, a

triangular wave any other periodic
waveform, the schmitt trigger will
produce a rectangular output that
has sharp leading and trailing
Schmitt-trigger transfer characteristic.
edges.

 Such fast rise and fall times are

desirable for all digital circuits.
 The value of Vi that causes
the output to jump from low
to high is called a positive-
going threshold voltage
VT+

 The value of Vi causing the

output to switch from high
to low is called the
negative-going threshold
voltage VT-

 The difference between the

two threshold voltages is
known as hysteresis
Schmitt trigger inverter.
Functional Parts of 555 Timer IC:
 555 Timer IC has basically three functional parts. They
are as follows:
 Comparator: It is used to compare two voltages at the
input level which is inverting (-) one and non inverting
(+). If the voltage at the non-inverting is higher than other
than the output is high. For ideal comparator input
resistance is infinite.
 Voltage Divider: As the input resistance is infinite in the
comparator so the voltage among all three resistors is
being divided equally. Value across each resistor is
Vin/3.
 Flip/Flop: Digital electronic device with memory. If the
input is high while low at R then the output at Q is high. It
means when S is high Q output is high and if R is high Q
output is low.
Pin Description of 555 Timer:
 Trigger Input: If the input <1/3Vcc than at that condition output
is high. It is useful in examining the timing capacitor discharging
in a stable circuit.
 Threshold Input: This pin is attached to the first comparator at
the non-inverting input terminal. If the threshold voltage is higher
than (2/3) Vcc than the output is high at the comparator thus
reset the output from high to low in the flip flop.
 Reset Input: As based on the internal condition of the flip-flop
this pin reset the output of the flip-flop. To get rid of any noise
interference an active low pin is attached to high state till any
reset operator is required. So for most of the time it is attached to
the supply voltage as in the figure.
 Control Input: An external voltage applied to this terminal
changes the threshold as well as trigger voltage. Thus by
imposing a voltage on this pin or by connecting a pot between
this pin and ground, the pulse width of the output wave can be
varied. when not used, the control pin should be bypassed to
ground with a 0.01uF capacitor to prevent any noise problem.
 Discharge Pin: When the timer output is low this
pin is connected to 0 volts. It is used to discharge
the timing capacitor in astable and monostable
mode.
 Ground: The reference point or ground point of
IC555 is connected to the ground terminal of the
dc voltage source, Voltages of the entire circuit are
measured with respect to this terminal.
 Output: The output of timer and the load is
connected to this pin.
 Supply: This voltage must be a pure ripple free
DC voltage which is obtained by connecting a
positive regulated power supply.
555 Timer - Astable
 Is a TTL-compatible integrated circuit (IC) that
can be used as an oscillator to provide a clock
waveform.
 It is basically a switching circuit that has two
distinct output levels, neither of the output levels
is stable.
 As a result the circuit switches back and forth
between these two unstable states.
 In other words, the circuit oscillates and the
output is a periodic, rectangular waveform.
 Since neither output is stable, this circuit is said
to be astable and is often referred to as a free-
running multivibrator or astable
multivibrator.
 The frequency of oscillation as well as the duty
cycle are accurately controlled by two external
+V CC
resistors and a single timing capacitor.
(4) (8)
R1 ---T---
RESET VCC
(7) t1 t2
DISCH

R2 (6) THRES (3)

OUT
(2) (5)
TRIG CONT
C1 GND
(1)
Internal diagram of Astable 555 timer
 Waveform for the Astable operation

 Voltage Across Timing

Capacitor
 In figure, the timing capacitor C is charged
toward +Vcc through RA and RB. The charging
time t1 is given as
t1 = 0.693 (RA + RB) C
This is the time during which the output is high.

 The timing capacitor C is then discharged

toward ground (GND) through the resistor RB.
The discharge time t2 is given as
t2 = 0.693 RB C
This is the time during which the output is low.
 The period T of the resulting clock waveform is
the sum of t1 and t2.
Thus, T = t1+ t2 = 0.693 ( RA + 2RB)C

 The frequency of oscillation is

f = 1 / T = 1.44 / ( RA + 2RB)C

 The output of 555 times connected in this way

outputs periodic rectangular wave but not the
square wave.
Because t1 and t2 are unequal.
So duty cycle = t2 / t1 + t2 = RB / RA + 2RB
555 Timer - Monostable
 A switching circuit having one stable state and
quasistable state.

 Since it has only one stable state, the circuit is

termed as monostable mutivibrator or simply
monostable.

 In stable state, the timing capacitor C is

completely discharged by means of an internal
transistor connected to C at pin 7. In this mode,
the output voltage at pin 3 is at ground potential.
 A negative pulse at the trigger input (pin 2) will
cause the circuit to switch to its quasistable
state.
 The output at pin 3 will go high and the
discharge transistor at pin 7 will turn off, thus
allowing the timing capacitor to begin charging
toward Vcc.
 When the voltage across C reaches 2/3 Vcc, the
circuit will regenerate back to its stable state.
 The discharge transistor will again turn on and
discharge C to GND, the output will go back to
GND, and the circuit will remain in this state until
another pulse arrives at the trigger input.
The output of the monostable can be considered
a positive pulse with a width
t = 1.1 RA C
Note: the input voltage at the trigger input must be
held at +Vcc, and the negative pulse should then
be applied when it is desired to trigger the circuit
into its quasistable or timing mode.
IC 555 as monostable multivibrator
 Monostable Nomograph
 By selecting suitable values
of C and R in the ranges of
0.001uF to 100uF and 1kΩ
to 10MΩ’s respectively, we
can read the expected
output frequency directly
from the nomograph graph
thereby eliminating any
error in the calculations.
 In practice the value of the
timing resistor for a
monostable 555 timer
should not be less than 1kΩ
or greater than 20MΩ
Operational Amplifiers
 Amplifier which could be configured to perform
variety of operations such as amplification,
addition, subtraction, differentiation, and
integration.
Hence the name operational amplifiers.
 Is basically a voltage amplifier with extremely
high voltage gain
Ex: 741 OP-AMP has a typical gain 2 x 105 or
106 dB.
Op-Amp Symbol

 The two input terminals are denoted as the

inverting and noninverting terminals
respectively.
 The inverting terminal is universally indicated by
a (-) symbol, and the noninverting terminal is
indicated by a (+) symbol.
Op-amp Parameter and Idealised
Characteristic
 Voltage gain = A = vo / v i
in decibels (dB) 20 log (A)

 Input impedance = Rin = vi / i i

 Differential input voltage = The difference

between the voltages at the non-inverting input
and the inverting input
vd = v+ - v-
 Open Loop Gain, (Avo)
Infinite – The main function of an operational amplifier is
to amplify the input signal and the more open loop gain it
has the better. Open-loop gain is the gain of the op-amp
without positive or negative feedback and for such an
amplifier the gain will be infinite but typical real values
range from about 20,000 to 200,000.

 Input impedance, (Zin)

Infinite – Input impedance is the ratio of input voltage to
input current and is assumed to be infinite to prevent any
current flowing from the source supply into the amplifiers
input circuitry ( Iin = 0 ). Real op-amps have input
leakage currents from a few pico-amps to a few milli-
amps.
 Output impedance, (Zout)
Zero – The output impedance of the ideal operational
amplifier is assumed to be zero acting as a perfect
internal voltage source with no internal resistance so that
it can supply as much current as necessary to the load.
This internal resistance is effectively in series with the
load thereby reducing the output voltage available to the
load. Real op-amps have output impedances in the 100-
20kΩ range.
 Bandwidth, (BW)
Infinite – An ideal operational amplifier has an infinite
frequency response and can amplify any frequency
signal from DC to the highest AC frequencies so it is
therefore assumed to have an infinite bandwidth. With
real op-amps, the bandwidth is limited by the Gain-
Bandwidth product (GB), which is equal to the frequency
where the amplifiers gain becomes unity.
 Inverting Amplifier
V - =0 ii

 In an inverting amplifier, ii + vf -
the output voltage
changes in an opposite
direction to the input
voltage.

 Assuming stable linear

operation, the differential
input voltage vd is forced
to be zero, or v - = v +.
 Since v+ = 0 because the noninverting terminal
is grounded, the inverting terminal is also forced
to be at ground potential; that is v- = 0.

 This condition is referred to as a virtual ground,

meaning that the inverting terminal is not really
connected to ground, but it acts as if it were
grounded from a voltage point of view.

 Since v- =0, the input voltage vi appears across

Ri. The input current ii is then
i i = vi / Ri
 The current ii flows to the junction point at the
amplifier inverting input terminal. However no
current can flow into or out of the amplifier, the
current must flow through Rf. A voltage vf is then
produced across Rf , given by
Vf = Rf ii = Rf . vi / Ri = Rf / Ri . vi

 Since the inverting input of the op-amp is at a

virtual ground, the output voltage is the voltage
across Rf, but with the reference positive
terminal on the left-hand side of Rf. This leads to
vo = - vf = - Rf / Ri .vi
 Let ACL represent the closed-loop voltage gain of
the circuit.
We have
ACL = vo / vi = - Rf / Ri

 Thus, the closed loop voltage gain is a simple

resistance ratio and is independent of the open
loop gain.
 Non-inverting amplifier
 In a non-inverting amplifier,
the output voltage changes
in the same direction as the
input voltage.
 Input signal is applied
directly to the noninverting
input.
 Assuming stable linear
operation, the differential
input voltage is forced to be
zero, and thus
v- = v+ = v i
 This voltage appears across the resistance Ri,
so the current ii is readily determined as
ii = vi / Ri
 Since no current flows into or out of the op-amp
inverting terminal, the current must be flowing
through the resistance Rf from the op-amp
output. A voltage vf appears across Rf and is
Vf = Rf ii = Rf vi / Ri
 The voltage vi with respect to ground, the
voltage vf, and the output voltage vo constitute a
closed loop, and a Kirchhoff voltage law
equation could be written if desired.
 It can be readily deduced that
vo = vi + vf = vi + Rf . vi = 1 + Rf vi
Ri Ri

The closed-loop voltage gain ACL is then given by

ACL = vo = 1 + Rf = Ri + Rf
vi Ri Ri
SLE
 MAGNITUDE COMPARATOR
 Magnitude comparator compares magnitude
two n-bit binary numbers, say X and Y and
activates one of these three outputs X=Y, X>Y
and X<Y.
Xn-1
Xn-2 ..
X0
. (X > Y) Input Output
n-bit X Y X>Y X=Y X<Y
(X = Y) X X<Y
Comparator
0 0 0 0 1
Yn-1 (X < Y) 0 1 0 1 0 X=Y
Yn-2 .. 1 0 1 0 0 X>Y
Y0
. 1 1 0 0 1 Y

(a) (b) (c)

a) Block diagram of Magnitude comparator (b) Truth table and (c) circuit for 1-
bit comparator
 MAGNITUDE COMPARATOR

X Y

X3 X2 X1 X0 Y3 Y2 Y1 Y0 X7 X6 X5 X4 Y7 Y6 Y 5 Y4 X3 X2 X1 X0 Y 3 Y 2 Y1 Y 0

+5v
15 13 12 10 1 14 11 9 15 13 12 10 1 14 11 9 15 13 12 10 1 14 11 9
4 (X > Y)in 4 4
IC 7485 3 (X = Y)in IC 7485 3 IC 7485 3
2 (X < Y)in 2 2
5 6 7 5 6 7 5 6 7
Vcc (16)
GND (8)
(X>Y)out (X=Y)out (X<Y)out (X>Y)out (X=Y)out (X<Y)out
(a) (b)

a) Functional diagram of IC 7485 and (b) 8-bit comparator from two

4-bit comparators.
Programmable Array Logic
 PAL is a programmable array of logic gates on a single chip.
 Programmable Array Logic
 Programming A PAL
 A PAL is different from a PROM because it has a programmable AND array and a fixed
OR array.

Y3=ABCD+ABCD+ABCD+ABCD
Y2=ABCD+ABCD+ABCD
Y1=ABC+ABC+ABC+ABC
Y0=ABCD
 Programmable Array Logic
 Commercially available PALs
 10H8: 10 input and 8 output AND-OR

 16H2: 6 input and 2 output AND-OR

 14L4: 14 input and 4 output AND-OR-

INVERT

For these chip numbers, H stands for active-

high output and L for active-low output.
 Programmable logic Arrays
 PLAs, along with ROMs and PALs, are included in more general
classification of ICs called programmable logic devices(PLDs).

PAL

PLA
 HDL implementation of data processing circuits

 Hardware design of multiplexers using Verilog code. The behavioral model

can be used to describe the 2 to 1 multiplexers in following different ways

module mux2to1(A,D0,D1,Y); module mux2to1(A,D0,D1,Y);

input A,D0,D1; // Circuit shown in Fig. 4-3(a) input A,D0,D1; // Circuit shown in Fig. 4-3(a)
output Y; output Y;
assign Y=(~A&D0)|(A&D1); assign Y= A ? D1 : D0; //Conditional assignment
endmodule endmodule

module mux2to1(A,D0,D1,Y); module mux2to1(A,D0,D1,Y);

input A,D0,D1; // Circuit shown in Fig. 4-3(a) input A,D0,D1; // Circuit shown in Fig. 4-3(a)
output Y; output Y;
reg Y; reg Y;
always @ (A or D0 or D1) always @ (A or D0 or D1)
if (A==1) Y=D1; case (A)
else Y=D0; 0 : Y=D0;
endmodule 1 : Y=D1;
endcase
endmodule
 Bus representation in HDL
 The Verilog code for demultiplexer/decoder.

module demux1to4(S,D,Y);
input [1:0] S;
input D;
output [3:0] Y;
reg [3:0] Y;
always @ (S or D)
case ({D,S}) //Concatenation of D and S to give 3 bits, D is MSB
3’b100 : Y= 4’b0001; //Binary representation, refer to Section 2-5. If D=1, S=00, Y=0001
3’b101 : Y= 4’b0010; // if D=1, S=01, Y=0010
3’b110 : Y= 4’b0100; // if D=1, S=10, Y=0100
3’b111 : Y= 4’b1000; // if D=1, S=11, Y=1000
default : Y= 4’b0000; //For other combinations D=0, then Y=0000
endcase
endmodule