CS152 – Computer Architecture and

Engineering

Lecture 7 – (Design Notebook+)

Single Cycle Control
2004-09-21
John Lazzaro
(www.cs.berkeley.edu/~lazzaro)

Dave Patterson
(www.cs.berkeley.edu/~patterson)

www-inst.eecs.berkeley.edu/~cs152/

CS 152 L07 Single Cycle 2 (1) UC Regents Fall 2004 © UCB

 Review
° 5 steps to design a processor
1. Analyze instruction set => datapath requirements
2. Select set of datapath components & establish clock methodology
3. Assemble datapath meeting the requirements
4. Analyze implementation of each instruction to determine setting of control
points that effects the register transfer.
5. Assemble the control logic (This Lecture)

° MIPS makes it easier

• Instructions same size; Source registers, immediates always in same place
• Operations always on registers/immediates

° Single cycle datapath => CPI=1, CCT => long

CS 152 L07 Single Cycle 2 (2) UC Regents Fall 2004 © UCB

 Why should you keep a design notebook?

° Keep track of the design decisions and the reasons

behind them
• Otherwise, it will be hard to debug and/or refine the design
• Write it down so that can remember in long project:
2 weeks ->2 yrs
• Others can review notebook to see what happened
° Record insights you have on certain aspect of the
design as they come up
° Record of the different design & debug experiments
• Memory can fail when very tired
° Industry practice: learn from others mistakes

CS 152 L07 Single Cycle 2 (3) UC Regents Fall 2004 © UCB

 Why do we keep it on-line?
° You need to force yourself to take notes!
• Open a window and leave an editor running while you work
1) Acts as reminder to take notes
2) Makes it easy to take notes
• 1) + 2) => will actually do it
° Take advantage of the window system’s
“cut and paste” features
° It is much easier to read your typing than your writing
° Also, paper log books have problems
• Limited capacity => end up with many books
• May not have right book with you at time vs. networked
screens
• Can use computer to search files/index files to find what
looking for

CS 152 L07 Single Cycle 2 (4) UC Regents Fall 2004 © UCB

 How should you do it?
° Keep it simple
• DON’T make it so elaborate that you won’t use (fonts, layout, ...)
° Separate the entries by dates
• type “date” command in another window and cut&paste
° Start day with problems going to work on today
° Record output of simulation into log with cut&paste; add
date
• May help sort out which version of simulation did what
° Record key email with cut&paste
° Record of what works & doesn’t helps team decide what
went wrong after you left
° Index: write a one-line summary of what you did at end of
each day

CS 152 L07 Single Cycle 2 (5) UC Regents Fall 2004 © UCB

On-line Notebook Example

°Refer to the handout

“Example of On-Line Log Book” on
CS 152 home page:
http://www-inst.eecs.berkeley.edu/~cs152/
handouts/online_notebook_example.html

CS 152 L07 Single Cycle 2 (6) UC Regents Fall 2004 © UCB

 Recap: Putting it All Together: 1 Cycle Datapath
Instruction<31:0>
Inst

<21:25>

<16:20>

<11:15>

<0:15>
Memory
Adr
Rs Rt Rd Imm16

PCSrc RegDst ALUctr MemWr MemtoReg

Zero
Rd Rt
1 0
Rs Rt
4 RegWr 5 5 5
Adder

busA
busW Rw Ra Rb
00

32 32-bit 32

ALU
Mux

32 Registers busB 32 0
PC

Clk 0

Mux
32

Mux
Adder

32 WrEn Adr
Extender

1 Data In
PC Ext

Data 1
Clk imm16 32
imm16

16 Memory
Clk

ExtOp ALUSrc
CS 152 L07 Single Cycle 2 (7) UC Regents Fall 2004 © UCB
 Recap: The MIPS-lite Subset
° ADD and subtract 31 26 21 16 11 6 0
• add rd, rs, rt op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
• sub rd, rs, rt
31 26 21 16 0
° OR Imm:
op rs rt immediate
• ori rt, rs, imm16 6 bits 5 bits 5 bits 16 bits

° LOAD and STORE

• lw rt, rs, imm16
• sw rt, rs, imm16
° BRANCH:
• beq rs, rt, imm16

CS 152 L07 Single Cycle 2 (8) UC Regents Fall 2004 © UCB

 Meaning of the Control Signals
° ExtOp: “zero”, “sign” ° MemWr: 1  write memory

° ALUsrc: 0  regB; 1  immed ° MemtoReg: 0  ALU; 1  Mem

° ALUctr: “add”, “sub”, “or” ° RegDst: 0  “rt”; 1  “rd”

° RegWr: 1  write register
RegDst
Zero ALUctr MemWr MemtoReg
Rd Rt
1 0
Rs Rt
RegWr 5 5 5
busA
busW Rw Ra Rb
32

ALU
32 32-bit
32 Registers busB 32 0
0

Mux
Clk
Mux
32
32 WrEn Adr
Extender

1
1 Data In
imm16 32 Data
16 Memory
Clk

ExtOp ALUSrc
CS 152 L07 Single Cycle 2 (9) UC Regents Fall 2004 © UCB
 Two equivalent ways to specify control
Control Control … Control AddU SubU ORI LW SW BEQ
line 0 line 1 line n Control A X
AddU A B line 0
Control
SubU line 1
ORI …
Control B Y
LW line n
SW
BEQ X Y (Rotate about 45degree axis)

°Book does left version (Fig 5.18, p. 308)

• Book combines all ALU instructions as
“R-format” vs. separate instructions (add …)
• Good news: lecture different view than book
°We’ll do right by committee, 1 at a time
CS 152 L07 Single Cycle 2 (10) UC Regents Fall 2004 © UCB
 Setting PC Source Control Signal
° PCSrc: 0  PC <= PC + 4
1  PC <= PC + 4 + {SignExt(Im16), 2’b00}
° Later in lecture: higher-level connection between mux and branch
cond
PCSrc Answer? AddU SubU ORI LW SW BEQ
0 0 0 0 0 0 0
Inst 1 0 0 0 0 0 1
Memory 2 0 0 0 0 1 1
Adr
4 3 0 0 0 1 1 1
Adder

4 0 0 1 1 1 1
5 0 1 1 1 1 1
00

6 1 1 1 1 1 1
Mux

PC

7 1 1 1 1 1 X
Adder

8 X X X X X 1
9 None of the above
imm16

Clk
PC Ext

CS 152 L07 Single Cycle 2 (11) UC Regents Fall 2004 © UCB

 Meaning of the Control Signals
° ExtOp: 0  “zero” ; 1  “sign” ° MemWr: 1  write memory

° ALUsrc: 0  regB; 1  immed ° MemtoReg: 0  ALU; 1  Mem

° ALUctr: “add”, “sub”, “or” ° RegDst: 0  “rt”; 1  “rd”

° RegWr: 1  write register
RegDst
Zero ALUctr MemWr MemtoReg
Rd Rt
1 0
Rs Rt
RegWr 5 5 5
busA
busW Rw Ra Rb
32

ALU
32 32-bit
32 Registers busB 32 0
0

Mux
Mux
32
Clk
32 WrEn Adr
Extender

1
1 Data In
imm16 32 Data
16 Memory
Clk

ExtOp ALUSrc
CS 152 L07 Single Cycle 2 (13) UC Regents Fall 2004 © UCB
 Specify ALU source mux Control
° ALUsrc: 0  reg as ALU B input; 1  immediate as ALU B input

Rd Rt
1 0 An swer? Ad dU SubU ORI LW SW BEQ
Rs Rt 0 0 0 0 0 0 0
5 5 5 1 0 0 0 0 0 1
busA 2 0 0 0 0 1 1
busW Rw Ra Rb
32 3 0 0 1 1 1 0

ALU
32 32-bit
32 Registers busB 0 4 0 0 0 1 1 1
5 0 0 0 1 1 X
Mux

32
Clk 32 6 1 1 1 1 1 1
Extender

1 Data In 7 1 1 1 1 1 X
imm16 32
16 8 X X X X X 1
9 None of t he above

ExtOp ALUSrc

CS 152 L07 Single Cycle 2 (14) UC Regents Fall 2004 © UCB

Administrivia
°COD Reading for next lecture: Sections
5.5 “Multicycle”, 5.6 “Microprogramming”
(on CD), “Fallacies and Pitfalls” 5.10
°Start Homework #2
°Lab 2 Verilog simulation Friday
°Find bugs in COD 3rd Edition?
• $1 reward to first person to report a bug
• Send email to cod3bugs@mkp.com
- Include Page number, line number on page,
BEFORE with bug, AFTER fix, why it’s a bug

CS 152 L07 Single Cycle 2 (16) UC Regents Fall 2004 © UCB

 Specify Immediate Extender Op Control
° ExtOp: 0  “zero extend immediate” ; 1  “sign extend imm.”

Rd Rt
1 0 Answer? AddU SubU ORI LW SW BEQ
Rs Rt 0 0 0 0 0 0 1
5 5 5 1 0 0 0 0 1 1
busA 2 0 0 0 1 1 1
busW Rw Ra Rb
32 3 0 0 1 1 1 1

ALU
32 32-bit
32 Registers busB 0 4 0 1 1 1 1 1
5 1 1 1 1 1 1
Mux

32
Clk 32 6 X 0 1 1 1 1
Extender

1 Data In 7 X X 0 1 1 1
imm16 32
16 8 X X 1 0 0 0
9 None of the above

ExtOp ALUSrc

CS 152 L07 Single Cycle 2 (17) UC Regents Fall 2004 © UCB

 Specify Register Write Control
° RegWr: 1  write register

RegDst Answer? AddU SubU ORI LW SW BEQ

Rd Rt 0 0 0 0 0 0 0
1 0 1 0 0 0 0 0 1
RegWr 5
Rs Rt 2 0 0 0 0 1 1
5 5
3 0 0 0 1 1 1
busA
busW Rw Ra Rb 4 0 0 1 1 1 1
32 5 0 1 1 1 1 1
ALU
32 32-bit
32 Registers busB 32
0 6 1 1 1 1 1 1
Mux

32 7 1 1 1 1 0 0
Clk
8 1 1 1 1 X X
Extender

1
imm16 32
9 None of the above
16

ExtOp ALUSrc

CS 152 L07 Single Cycle 2 (19) UC Regents Fall 2004 © UCB

 Specify Register Destination Control
° RegDst: 0  “rt”; 1  “rd”
31 26 21 16 11 6 0
op rs rt rd shamt funct
RegDst 31 26 21 16 0
Rd Rt op rs rt immediate
1 0
Rs Rt Answer? AddU SubU ORI LW SW BEQ
RegWr 5 5 5
0 0 0 0 0 0 0
busA
busW Rw Ra Rb 1 0 0 0 0 0 1
32 2 0 0 0 0 1 1
ALU
32 32-bit
32 Registers busB 3 0 0 0 1 1 0
0
Mux

32 4 0 0 1 1 0 0
Clk
5 0 1 1 0 0 0
Extender

1
imm16 6 1 1 0 0 0 0
32
16 7 1 1 0 0 X X
8 1 1 0 0 0 X
9 None of the above
ExtOp ALUSrc

CS 152 L07 Single Cycle 2 (21) UC Regents Fall 2004 © UCB

 Specify the Memory Write Control Signal
° MemWr: 1  write memory
RegDst
Zero ALUctr MemWr MemtoReg
Rd Rt
1 0
Rs Rt
RegWr 5 5 5
busA
Rw Ra Rb
32

ALU
32 32-bit
32 Registers busB 32 0
0

Mux
Mux

32
Answer? AddU SubU ORI LW SW BEQ
Clk busW 32 WrEn Adr 0 0 0 0 0 0 0
Extender

1
1 Data In 1 0 0 0 0 0 1
imm16 32 Data
16 2 0 0 0 0 1 0
Memory 3 0 0 0 1 0 0
Clk
4 0 0 1 0 0 0
5 0 1 0 0 0 0
ExtOp ALUSrc 6 1 0 0 0 0 0
7 0 0 0 0 1 X
8 X X X 0 1 X
9 None of the above

CS 152 L07 Single Cycle 2 (23) UC Regents Fall 2004 © UCB

Specify Memory To Register File Mux Control
° MemtoReg: 0  ALU; 1  Mem
RegDst
Zero ALUctr MemWr MemtoReg
Rd Rt
1 0
Rs Rt
RegWr 5 5 5
busA
Rw Ra Rb
32

ALU
32 32-bit
32 Registers busB 32 0
0

Mux
Mux

32
Answer? AddU SubU ORI LW SW BEQ
Clk busW 32 WrEn Adr 0 0 0 0 0 0 0
Extender

1
1 Data In 1 0 0 0 0 0 1
imm16 32 Data 2 0 0 0 0 1 0
16 Memory
Clk 3 0 0 0 1 0 X
4 0 0 0 1 X X
5 0 1 0 0 0 0
ExtOp ALUSrc 6 1 0 0 0 0 0
7 0 0 0 0 1 X
8 0 0 0 1 0 X
9 None of the above

CS 152 L07 Single Cycle 2 (25) UC Regents Fall 2004 © UCB

 Specify the ALU Control Signals
° ALUctr: 0  “add”, 1  “sub”, 2  “or”
RegDst
Zero ALUctr MemWr MemtoReg
Rd Rt
1 0
Rs Rt
RegWr 5 5 5
busA
Rw Ra Rb
32

ALU
32 32-bit
32 Registers busB 32 0
0

Mux
Mux

32
Answer? AddU SubU ORI LW SW BEQ
Clk busW 32 WrEn Adr 0 0 0 0 0 0 0
Extender

1
1 Data In 1 0 0 0 0 0 1
imm16 32 Data
16 2 0 1 0 0 0 1
Memory
Clk 3 0 1 2 0 0 1
4 0 1 2 0 0 X
5 0 1 2 0 X X
ExtOp ALUSrc 6 0 1 2 X X X
7 X 1 2 X X X
8 X X 2 0 0 1
9 None of the above

CS 152 L07 Single Cycle 2 (27) UC Regents Fall 2004 © UCB

 The Add Instruction
31 26 21 16 11 6 0
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

° add rd, rs, rt

• mem[PC] Fetch the instruction

from memory

• R[rd] <= R[rs] + R[rt] The actual operation

• PC <= PC + 4 Calculate the next

instruction’s address

CS 152 L07 Single Cycle 2 (29) UC Regents Fall 2004 © UCB

 Instruction Fetch Unit at the Beginning of Add
° Fetch the instruction from Instruction memory:
Instruction <= mem[PC]
• This is the same for all instructions

Inst Instruction<31:0>
Memory
Adr

PCSrc

4
Adder

00
Mux

PC
Adder
imm16

Clk
PC Ext

CS 152 L07 Single Cycle 2 (30) UC Regents Fall 2004 © UCB

 Instruction
31
Fetch
26 21
Unit
16
at the End of Branch
0
op rs rt immediate
if (Zero == 1) PC = PC + 4 + {SignExt[imm16], 2’b00} ;
else PC = PC + 4
Inst
Memory Instruction<31:0>
PCSrc Adr
° What is encoding of PCSrc?
Zero
• Direct MUX select?
• Branch / not branch
PCSrc
° Let’s choose second option
4
Adder

PCSrc zero? MUX

00

0
0 X 0
Mux

PC

1 0 0
Adder

1
1 1 1
imm16

Clk

CS 152 L07 Single Cycle 2 (31) UC Regents Fall 2004 © UCB

 The Single Cycle Datapath during Load
31 26 21 16 0
op rs rt immediate

° R[rt] <= Data Memory [R[rs] + SignExt[imm16]]

Instruction<31:0>
PCSrc<= +4
Instruction

<21:25>

<16:20>

<11:15>

<0:15>
Rd Rt Fetch Unit
RegDst = 0 Clk
1 Mux 0
Rs Rt ALUctr Rt Rs Rd Imm16
RegWr <= 1 5 5 5 <= Add MemtoReg <= 1
busA Zero MemWr = 0
Rw Ra Rb
busW 32

ALU
32 32-bit
32 0
Registers busB 0 32

Mux
Clk
Mux

32
WrEn Adr 1
Extender

1 Data In 32
imm16 Data 32
32
16 Memory
Clk
ALUSrc = 1

ExtOp <= 1
CS 152 L07 Single Cycle 2 (32) UC Regents Fall 2004 © UCB
 The Single Cycle Datapath during Store
31 26 21 16 0
op rs rt immediate

° Data Memory [R[rs] + SignExt[imm16]] <= R[rt]

Instruction<31:0>
PCSrc <=
Instruction

<21:25>

<16:20>

<11:15>

<0:15>
Rd Rt Fetch Unit
RegDst <= Clk
1 Mux 0
Rs Rt ALUctr <= Rt Rs Rd Imm16
RegWr <= 5 5 5
MemtoReg <=
busA Zero MemWr <=
Rw Ra Rb
busW 32

ALU
32 32-bit
32 0
Registers busB 0 32

Mux
Clk
Mux
32
32
WrEn Adr 1
Extender

1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc <=

ExtOp <=
CS 152 L07 Single Cycle 2 (33) UC Regents Fall 2004 © UCB
 The Single Cycle Datapath during Store
31 26 21 16 0
op rs rt immediate

° Data Memory [R[rs] + SignExt[imm16]] <= R[rt]

Instruction<31:0>
PCSrc<= +4
Instruction

<21:25>

<16:20>

<11:15>

<0:15>
Rd Rt Fetch Unit
RegDst <= x Clk
1 Mux 0
Rs Rt ALUctr Rt Rs Rd Imm16
RegWr <= 0 5 5 5 <= Add
MemtoReg <= x
busA Zero MemWr <= 1
Rw Ra Rb
busW 32

ALU
32 32-bit
32 0
Registers busB 0 32

Mux
Clk
Mux

32
32
WrEn Adr 1
Extender

1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc <= 1

ExtOp <= 1
CS 152 L07 Single Cycle 2 (34) UC Regents Fall 2004 © UCB
 The Single Cycle Datapath during Branch
31 26 21 16 0
op rs rt immediate

if (R[rs] - R[rt] == 0) Zero <= 1 ; else Zero <= 0

Instruction<31:0>
PCSrc<= “Br”
Instruction

<21:25>

<16:20>

<11:15>

<0:15>
Rd Rt Fetch Unit
RegDst <= x Clk
1 Mux 0
RegWr <= 0 Rs Rt ALUctr <=Sub Rt Rs Rd Imm16
5 5 5 MemtoReg <= x
busA Zero MemWr <= 0
Rw Ra Rb
busW 32

ALU
32 32-bit
32 0
Registers busB 0 32

Mux
Clk
Mux

32
32
WrEn Adr 1
Extender

1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc <= 0

ExtOp <= x
CS 152 L07 Single Cycle 2 (35) UC Regents Fall 2004 © UCB
Step 4: Given Datapath: RTL -> Control
Instruction<31:0>

<21:25>

<21:25>

<16:20>

<11:15>
Inst

<0:15>
Memory
Adr
Op Fun Rt Rs Rd Imm16

Control

PCSrc RegWr RegDst ExtOp ALUSrc ALUctr MemWr MemtoReg Zero

DATA PATH

CS 152 L07 Single Cycle 2 (36) UC Regents Fall 2004 © UCB

 A Summary of Control Signals

inst Register Transfer

ADD R[rd] <= R[rs] + R[rt]; PC <= PC + 4
ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, PCSrc = “+4”
SUB R[rd] <= R[rs] – R[rt]; PC <= PC + 4
ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, PCSrc = “+4”
ORi R[rt] <= R[rs] + zero_ext(Imm16); PC <= PC + 4
ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, PCSrc = “+4”
LOAD R[rt] <= MEM[ R[rs] + sign_ext(Imm16)]; PC <= PC + 4
ALUsrc = Im, Extop = “Sn”, ALUctr = “add”,
MemtoReg, RegDst = rt, RegWr, PCSrc = “+4”
STORE MEM[ R[rs] + sign_ext(Imm16)] <= R[rs]; PC <= PC + 4
ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, PCSrc = “+4”
BEQ if ( R[rs] == R[rt] ) then PC <= PC +4 + {sign_ext(Imm16)], 00’b2} else PC <= PC + 4
PCSrc = “Br”, ALUctr = “sub”

CS 152 L07 Single Cycle 2 (37) UC Regents Fall 2004 © UCB

 A Summary of the Control Signals
See func 10 0000 10 0010 We Don’t Care :-)
Appendix A op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100
add sub ori lw sw beq
RegDst 1 1 0 0 x x
ALUSrc 0 0 1 1 1 0
MemtoReg 0 0 0 1 x x
RegWrite 1 1 1 1 0 0
MemWrite 0 0 0 0 1 0
PCSrc 0 0 0 0 0 1
ExtOp x x 0 1 1 x
ALUctr<2:0> Add Subtract Or Add Add Subtract

31 26 21 16 11 6 0
R-type op rs rt rd shamt funct add, sub

I-type op rs rt immediate ori, lw, sw, beq

J-type op target address jump

CS 152 L07 Single Cycle 2 (38) UC Regents Fall 2004 © UCB

How to implement control in Verilog?

°Need to set control lines based on

instruction
°Which statement in Verilog good for
doing different operations depending
on value in a field of a word?
case (selector)
item {, item} : statement;
item {, item} : statement;
default : statement
endcase

CS 152 L07 Single Cycle 2 (39) UC Regents Fall 2004 © UCB

The Single Cycle Datapath during Or Immediate
31 26 21 16 0
op rs rt immediate

° R[rt] <= R[rs] or ZeroExt[Imm16]

Instruction<31:0>
PCSrc <= +4
Instruction

<21:25>

<16:20>

<11:15>

<0:15>
Rd Rt Fetch Unit
RegDst <= 0 Clk
1 Mux 0
Rs Rt ALUctr <= Or Rt Rs Rd Imm16
RegWr <= 1 5 5 5 MemtoReg <= 0
busA Zero MemWr <= 0
Rw Ra Rb
busW 32

ALU
32 32-bit
32 0
Registers busB 0 32

Mux
Clk
Mux

32
32
WrEn Adr 1
Extender

1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc <= 1

ExtOp <= 0
CS 152 L07 Single Cycle 2 (40) UC Regents Fall 2004 © UCB
Example for OR immediate case
case (Instruction<31:25>)
13 /* ORi */ :
begin
RegDst = 0;
ALUSrc = 1;
MemtoReg = 0;
RegWrite = 1;
MemWrite = 0;
PCSrc = 0;
ExtOp = 0;
ALUctr = 2’b10;
end
…
default : statement
endcase
CS 152 L07 Single Cycle 2 (41) UC Regents Fall 2004 © UCB
 Specify all control in one assignment
case (Instruction<31:25>)
13 /* ORi */ :
{RegDst,ALUSrc,MemtoReg,
RegWrite,MemWrite,PCSrc,Jump,
ExtOp,ALUctr}
= {1’b0, 1’b1, 1’b0, 1’b1,
1’b0, 1’b0, 1’b0, 2’b01};
…

default : statement
endcase

CS 152 L07 Single Cycle 2 (42) UC Regents Fall 2004 © UCB

 Better way than specify as 0s and 1s
°Hard to read and understand
• Easy to make mistakes; Alternative?
°Associate Names with control values!
parameter RegDstRt=0, RegDstRd=1,
ALUSrcBReg = 0, ALUSrcBImm = 1,
RegValALU = 0, RegValMem = 1,
RegWr = 1, NoRegWr = 0,
MemWr = 1, NoMemWr = 0,
PCSrc4 = 0, PCSrcBr = 1,
ZeroExt = 0, SignExt = 1,
Add = 0, Sub = 1, Or = 2;

CS 152 L07 Single Cycle 2 (43) UC Regents Fall 2004 © UCB

 Specify all control symbolically
case (Instruction<31:25>)

13 /* ORi */ :
{RegDst,ALUSrc,MemtoReg,
RegWrite,MemWrite,PCSrc,Jump,
ExtOp,ALUctr}
= {RegDstRt, ALUSrcBImm,
RegValALU, RegWr, NoMemWr,
PCSrc4, ZeroExt, Or};
…
default : statement
endcase

CS 152 L07 Single Cycle 2 (44) UC Regents Fall 2004 © UCB

Local Decoding: R-type v. Add + Sub
op 00 0000 00 1101 10 0011 10 1011 00 0100
R-type ori lw sw beq
RegDst 1 0 0 x x
ALUSrc 0 1 1 1 0
MemtoReg 0 0 1 x x
RegWrite 1 1 1 0 0
MemWrite 0 0 0 1 0
Branch 0 0 0 0 1
Jump 0 0 0 0 0
ExtOp x 0 1 1 x
ALUop<N:0> “R-type” Or Add Add Subtract

func
ALU ALUctr
op Main 6
ALUop Control 3
6 Control
(Local)
N

ALU
CS 152 L07 Single Cycle 2 (45) UC Regents Fall 2004 © UCB
 The Encoding of ALUop
func
op 6 ALU ALUctr
Main
ALUop Control
6 Control 3
(Local)
N
° In this exercise, ALUop has to be 2 bits wide to
represent:
• (1) “R-type” instructions
• “I-type” instructions that require the ALU to perform:
- (2) Or, (3) Add, and (4) Subtract
R-type ori lw sw beq
ALUop (Symbolic) “R-type” Or Add Add Subtract
ALUop<1:0> 11 10 00 00 01

° To implement more of MIPS ISA, ALUop has to be

bigger to represent more (4 bits in book to add NOR):
• (1) “R-type” instructions
• “I-type” instructions that require the ALU to perform:
- (2) Or, (3) Add, (4) Subtract, and (5) Nor (Example: nor)
CS 152 L07 Single Cycle 2 (46) UC Regents Fall 2004 © UCB
 Drawback of this Single Cycle Processor
°Long cycle time:
• Cycle time must be long enough for the
load instruction:
PC’s Clock -to-Q +
Instruction Memory Access Time +
Register File Access Time +
ALU Delay (address calculation) +
Data Memory Access Time +
Register File Setup Time +
Clock Skew

°Cycle time for load is much longer than

needed for all other instructions
CS 152 L07 Single Cycle 2 (47) UC Regents Fall 2004 © UCB
 Preview
Next Time:
°MultiCycle Data Path
•CPI  1, CycleTime much shorter
(~1/5 of time)

CS 152 L07 Single Cycle 2 (48) UC Regents Fall 2004 © UCB

 Summary
° Single cycle datapath => CPI=1, CCT => long

° 5 steps to design a processor

• 1. Analyze instruction set => datapath requirements
• 2. Select set of datapath components & establish clock methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to determine setting of
control points that effects the register transfer.
• 5. Assemble the control logic
Processor
Input
° Control is the hard part Control
Memory
° MIPS makes control easier
Datapath
• Instructions same size Output
• Source registers always in same place
• Immediates same size, location
• Operations always on registers/immediates

CS 152 L07 Single Cycle 2 (49) UC Regents Fall 2004 © UCB

 Where to get more information?

° Chapter 5.1 to 5.4 of your text book:

• David Patterson and John Hennessy, “Computer
Organization & Design: The Hardware / Software
Interface,” Third Edition, Morgan Kaufman
Publishers, San Mateo, California, 2003.
° One of the best PhD thesis on processor
design:
• Manolis Katevenis, “Reduced Instruction Set
Computer Architecture for VLSI,” PhD
Dissertation, EECS, U C Berkeley, 1982.
° For a reference on the MIPS architecture:
• Gerry Kane, Joe Heinrich “MIPS RISC
Architecture,” Prentice Hall, 2nd edition, 1992
CS 152 L07 Single Cycle 2 (50) UC Regents Fall 2004 © UCB
Bonus Slides

°The following slides show how to go

from tables that describe inputs and
control lines into gates
°Can be done by CAD tools instead of
by hand for 2-level logic equations
very efficiently

CS 152 L07 Single Cycle 2 (51) UC Regents Fall 2004 © UCB

 The Truth Table for ALUctr
funct<3:0> Instruction Op.
0000 add
ALUop R-type ori lw sw beq 0010 subtract
(Symbolic) “R-type” Or Add Add Subtract 0100 and
ALUop<2:0> 1 00 0 10 0 00 0 00 0 01 0101 or
1010 set-on-less-than

ALUop func ALU ALUctr

bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> Operation bit<2> bit<1> bit<0>
0 0 0 x x x x Add 0 1 0
0 x 1 x x x x Subtract 1 1 0
0 1 x x x x x Or 0 0 1
1 x x 0 0 0 0 Add 0 1 0
1 x x 0 0 1 0 Subtract 1 1 0
1 x x 0 1 0 0 And 0 0 0
1 x x 0 1 0 1 Or 0 0 1
1 x x 1 0 1 0 Set on < 1 1 1

CS 152 L07 Single Cycle 2 (52) UC Regents Fall 2004 © UCB

 The Logic Equation for ALUctr<2>
ALUop func
bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<2>
0 x 1 x x x x 1
1 x x 0 0 1 0 1
1 x x 1 0 1 0 1

This makes func<3> a don’t care

° (ALUctr<2> = ! ALUop<2>) & ALUop<0> +

ALUop<2> & !func<2> & func<1> & !func<0>

CS 152 L07 Single Cycle 2 (53) UC Regents Fall 2004 © UCB

 The Logic Equation for ALUctr<1>
ALUop func
bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<1>
0 0 0 x x x x 1
0 x 1 x x x x 1
1 x x 0 0 0 0 1
1 x x 0 0 1 0 1
1 x x 1 0 1 0 1

° (ALUctr<1> = !ALUop<2>) & !ALUop<1> +

ALUop<2> & !func<2> & !func<0>

CS 152 L07 Single Cycle 2 (54) UC Regents Fall 2004 © UCB

 The Logic Equation for ALUctr<0>
ALUop func
bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<0>
0 1 x x x x x 1
1 x x 0 1 0 1 1
1 x x 1 0 1 0 1

° ALUctr<0> = !ALUop<2> & ALUop<1>

+ ALUop<2> & !func<3> & func<2> &
!func<1> & func<0>
+ ALUop<2> & func<3> & !func<2> &
func<1> & !func<0>

CS 152 L07 Single Cycle 2 (55) UC Regents Fall 2004 © UCB

 The ALU Control Block
func
6 ALU ALUctr
ALUop Control
3
(Local)
3

° ALUctr<2> = !ALUop<2> & ALUop<0> +

ALUop<2> & !func<2> & func<1> & !func<0>
° ALUctr<1> = !ALUop<2> & !ALUop<1> +
ALUop<2> & !func<2> & !func<0>
° ALUctr<0> = !ALUop<2> & ALUop<1>
+ ALUop<2> & !func<3> & func<2> & !func<1> & func<0>
+ ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

CS 152 L07 Single Cycle 2 (56) UC Regents Fall 2004 © UCB

 Step 5: Logic for each control signal

° PCSrc <= (OP == `BEQ) ? `Br : `plus4;

° ALUsrc <= (OP == `Rtype) ? `regB : `immed;
° ALUctr <= (OP == `Rtype`) ? funct :
(OP == `ORi) ? `ORfunction :
(OP == `BEQ) ? `SUBfunction :
`ADDfunction;
° ExtOp <= _____________
° MemWr <= _____________
° MemtoReg <= _____________
° RegWr: <=_____________
° RegDst: <= _____________

CS 152 L07 Single Cycle 2 (57) UC Regents Fall 2004 © UCB

 Step 5: Logic for each control signal

° PCSrc <= (OP == `BEQ) ? `Br : `plus4;

° ALUsrc <= (OP == `Rtype) ? `regB : `immed;
° ALUctr <= (OP == `Rtype`) ? funct :
(OP == `ORi) ? `ORfunction :
(OP == `BEQ) ? `SUBfunction :
`ADDfunction;
° ExtOp <= (OP == `ORi) : `ZEROextend : `SIGNextend;
° MemWr <= (OP == `Store) ? 1 : 0;
° MemtoReg <= (OP == `Load) ? 1 : 0;
° RegWr: <= ((OP == `Store) || (OP == `BEQ)) ? 0 : 1;
° RegDst: <= ((OP == `Load) || (OP == `ORi)) ? 0 : 1;

CS 152 L07 Single Cycle 2 (58) UC Regents Fall 2004 © UCB

The “Truth Table” for the Main Control
RegDst
func
ALUSrc ALU ALUctr
op Main 6
6 Control
: Control 3
ALUop (Local)
3
op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
R-type ori lw sw beq jump
RegDst 1 0 0 x x x
ALUSrc 0 1 1 1 0 x
MemtoReg 0 0 1 x x x
RegWrite 1 1 1 0 0 0
MemWrite 0 0 0 1 0 0
PCSrc 0 0 0 0 1 0
Jump 0 0 0 0 0 1
ExtOp x 0 1 1 x x
ALUop (Symbolic) “R-type” Or Add Add Subtract xxx
ALUop <2> 1 0 0 0 0 x
ALUop <1> 0 1 0 0 0 x
ALUop <0> 0 0 0 0 1 x

CS 152 L07 Single Cycle 2 (59) UC Regents Fall 2004 © UCB

 The “Truth Table” for RegWrite
op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
R-type ori lw sw beq jump
RegWrite 1 1 1 0 0 0

° RegWrite = R-type + ori + lw

= !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0> (R-type)
+ !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0> (ori)
+ op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0> (lw)

op<5> .. op<5> .. op<5> .. op<5> .. op<5> .. op<5>..

<0> <0> <0> <0> <0> op<0>

R-type ori lw sw beq jump

RegWrite

CS 152 L07 Single Cycle 2 (60) UC Regents Fall 2004 © UCB

 PLA Implementation of the Main Control
op<5> .. op<5> .. op<5> .. op<5> .. op<5> .. op<5>..
<0> <0> <0> <0> <0> op<0>

R-type ori lw sw beq jump

RegWrite

ALUSrc
RegDst
MemtoReg
MemWrite
Branch
Jump
ExtOp
ALUop<2>
ALUop<1>
ALUop<0>

CS 152 L07 Single Cycle 2 (61) UC Regents Fall 2004 © UCB

A Real MIPS Datapath (CNS T0)

CS 152 L07 Single Cycle 2 (62) UC Regents Fall 2004 © UCB

 Putting it All Together: A Single Cycle Processor
ALUop
ALU ALUctr
RegDst 3 func Control
op Main 3
ALUSrc Instr<5:0> 6
6 Control
Instr<31:26> : Instruction<31:0>
PCSrc
Instruction

<21:25>

<16:20>

<11:15>

<0:15>
Rd Rt Fetch Unit
RegDst Clk
1 Mux 0
Rs Rt Rt Rs Rd Imm16
RegWr 5 5 5 ALUctr
busA Zero MemWr MemtoReg
Rw Ra Rb
busW 32

ALU
32 32-bit
32 0
Registers busB 0 32

Mux
Clk
Mux

32
32
WrEn Adr 1
Extender

1 Data In 32
imm16 Data
32
Instr<15:0> 16 Memory
Clk
ALUSrc

ExtOp
CS 152 L07 Single Cycle 2 (63) UC Regents Fall 2004 © UCB