Hardware and Software

Subsystems of Mixed-Signal
Architectures – Part III

Alex Doboli, Ph.D.

Department of Electrical and Computer Engineering
State University of New York at Stony Brook
Email: adoboli@ece.sunysb.edu

©Alex Doboli 2006

System Buses

• Buses interconnect GIOPs to microcontroller, analog blocks,

digital blocks, clocking

• System buses influence

– System latency
– Energy & power consumption

T data com = T delay + T busy waiting

T delay = rc L2 / 2 (Elmore delay)

©Alex Doboli 2006

System Buses

©Alex Doboli 2006

System Buses

©Alex Doboli 2006

System Buses

• Port connections for GIO & GOO

©Alex Doboli 2006

System Buses

• Port connections for GIE

©Alex Doboli 2006

System Buses

©Alex Doboli 2006

System Buses

• Related registers: GDI_I_ON, GDI_E_IN, GDI_O_OU, GDI_E_OU

Register Bit 7 Bit 6 Bit 5 Bit 4

GDI_O_IN 0 NOC NOC NOC NOC

GDI_O_IN 1 GIO[7]-> GIO[6]-> GIO[5]-> GIO[4]->
GOO[7] GOO[6] GOO[5] GOO[4]

GDI_E_IN 0 NOC NOC NOC NOC

GDI_E_IN 1 GIE[7]-> GIE[6]-> GIE[5]-> GIE[4]->
GOE[7] GOE[6] GOE[5] GOE[4]

©Alex Doboli 2006

System Buses

• Related registers: GDI_I_ON, GDI_E_IN, GDI_O_OU, GDI_E_OU

Register Bit 3 Bit 2 Bit 1 Bit 0

GDI_O_IN 0 NOC NOC NOC NOC

GDI_O_IN 1 GIO[3]-> GIO[2]-> GIO[1]-> GIO[0]->
GOO[3] GOO[2] GOO[1] GOO[0]

GDI_E_IN 0 NOC NOC NOC NOC

GDI_E_IN 1 GIE[3]-> GIE[2]-> GIE[1]-> GIE[0]->
GOE[3] GOE[2] GOE[1] GOE[0]

©Alex Doboli 2006

 System Buses

• Related registers: GDI_I_ON, GDI_E_IN, GDI_O_OU, GDI_E_OU

Register Bit 7 Bit 6 Bit 5 Bit 4

GDI_O_OU 0 NOC NOC NOC NOC

GDI_O_OU 1 GOO[7]-> GOO[6]-> GOO[5]-> GOO[4]->
GIO[7] GIO[6] GIO[5] GIO[4]

GDI_E_OU 0 NOC NOC NOC NOC

GDI_E_OU 1 GOE[7]-> GOE[6]-> GOE[5]-> GOE[4]->
GIE[7] GIE[6] GIE[5] GIE[4]

©Alex Doboli 2006

 System Buses

• Related registers: GDI_I_ON, GDI_E_IN, GDI_O_OU, GDI_E_OU

Register Bit 3 Bit 2 Bit 1 Bit 0

GDI_O_OU 0 NOC NOC NOC NOC

GDI_O_OU 1 GOO[3]-> GOO[2]-> GOO[1]-> GOO[0]->
GIO[3] GIO[2] GIO[1] GIO[0]

GDI_E_OU 0 NOC NOC NOC NOC

GDI_E_OU 1 GOE[3]-> GOE[2]-> GOE[1]-> GOE[0]->
GIE[3] GIE[2] GIE[1] GIE[0]

©Alex Doboli 2006

Row Digital Interconnect (RDI)

©Alex Doboli 2006

Introduction to
Embedded Mixed-Signal Systems

©Alex Doboli 2006

Introduction to
Embedded Mixed-Signal Systems

©Alex Doboli 2006

Row Digital Interconnect (RDI)

Routing of signals to digital block inputs:

• DATA (primary input):
 RI (4 bits)
 RO (block outputs)
 Broadcast: BCROW, keeper (flip-flop)
 ACMP (comparator outputs)
 Input of the previous block
 High, Low

• AUX (auxiliary input):

 RI (4 bits)

• RO (primary output):
 RO (4 bits)
 GOO
 GOE
©Alex Doboli 2006
Row Digital Interconnect (RDI)

Routing of signals to digital block inputs:

• CLK (separate for each digital block):
SYSCLKX2
CLK32
VC1, VC2, VC3
 Broadcast
RI
 RO
 Low, High
 CLK of previous digital block

• Chaining (increase bit-width of blocks):

 FPB
 TPB
 FNB
 TNB
©Alex Doboli 2006
Row Digital Interconnect (RDI)

©Alex Doboli 2006

Row Digital Interconnect (RDI)

©Alex Doboli 2006

Row Digital Interconnect (RDI)

• Registers involved in RDI programming: RDI_RI, RDI_SYN,

RDI_IS, RDI_LT, RDI_RO

• Register RDI_RI:
– Controls the input that drives the RI of a row
– RDI0RI (row 0), RDI1RI (row 1), RDI2RI (row 2), RDI3RI (row 3)
– 2 bits (4 sources) for each RI bit

• Register RDI_SYN:
– Synchronization of the RDI sources
– RDI0SYN (row 0), RDI1SYN (row 1), RDI2SYN (row 2),
RDI3SYN (row 3)
– Synchronization between “No synchronization” or
SYSCLOCK

©Alex Doboli 2006

Row Digital Interconnect (RDI)

• Registers involved in RDI programming: RDI_RI, RDI_SYN,

RDI_IS, RDI_LT, RDI_RO

• Register RDI_IS:
– Defines broadcast signal and inputs to LUT to RO
– One register per row: RDI0IS, RDI1IS, RDI2IS, RDI3IS
– Inputs to LUT are RI or RO

• Registers RDI_LT:
– Logic equations programmed through RDILT0 and RDILT1
– 2 registers per row: RDI0LT0, RDI0LT1, …
– 4 LUTs per row

©Alex Doboli 2006

Row Digital Interconnect (RDI)

Value Logic function Value Logic function

0000 FALSE 1000 A NOR B

0001 A AND B 1001 A XNOR B

0010 A AND B 1010 B

0011 A 1011 A OR B

0100 A AND B 1100 A

0101 B 1101 A OR B

0110 A XOR B 1110 A NAND B

0111 A OR B 1111 TRUE

©Alex Doboli 2006

Row Digital Interconnect (RDI)

• Registers involved in RDI programming: RDI_RI, RDI_SYN,

RDI_IS, RDI_LT, RDI_RO

• Register RDI_RO:
– LUT outputs connected to GOO and GOE
– One register per row (RDI0RO0 & RDI1RO0, …)

©Alex Doboli 2006

Analog Interconnect

©Alex Doboli 2006

Analog Interconnect

Analog bus

Comparator output
Comparator bus

NMUX

OpAmp output

PMUX Local connect.

RBotMux
©Alex Doboli 2006
Local Interconnect (CT blocks)
• NMUX connections:

• PMUX connections:

• RBotMUX connections:

©Alex Doboli 2006

Analog Interconnect

C inputs

A inputs
OpAmp output

Analog bus

Comparator bus
B inputs

©Alex Doboli 2006

Local Interconnect (SC blocks)
• A input connections:

• B input connections:

©Alex Doboli 2006

Local Interconnect (SC blocks)

• C input connections:

©Alex Doboli 2006

Input port connections

©Alex Doboli 2006

Input Port Connections

• Registers involved in Input port programming:

– Register AMX_IN (controls MUXes ACMx)
– Register ABF_CR0 (controls MUXes ACx)

Value Bits 7-6 Bits 5-4 Bits 3-2 Bits 1-0

00 P0[0] -> P0[1] -> P0[1] -> P0[1] ->

ACM3 ACM2 ACM1 ACM0
01 P0[2] -> P0[3] -> P0[2] -> P0[3] ->
ACM3 ACM2 ACM1 ACM0
10 P0[4] -> P0[5] -> P0[4] -> P0[5] ->
ACM3 ACM2 ACM1 ACM0
11 P0[6] -> P0[7] -> P0[6] -> P0[7] ->
ACM3 ACM2 ACM1 ACM0

©Alex Doboli 2006

Output Port Connections

©Alex Doboli 2006

Output Port Connections

• Registers involved in Output Port connection programming:

– Register ABF_CR0:
• Enables output buffers for analog columns
• Bypass OpAmp (positive OpAmp input to output)
• Power level of output buffers

©Alex Doboli 2006