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VLSI

Design

CMOS Transistor Theory


Outline
 Introduction
 MOS Capacitor
 nMOS I-V Characteristics
 pMOS I-V Characteristics
 Gate and Diffusion Capacitance
 Pass Transistors
 RC Delay Models

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CMOS Transistor
VLSI Design Theory 2
Introduction
 So far, we have treated transistors as ideal switches
 An ON transistor passes a finite amount of current
Depends on terminal voltages
 Derive current-voltage (I-V) relationships
 Transistor gate, source, drain all have capacitance
 I = C (DV/Dt) -> Dt = (C/I) DV
 Capacitance and current determine speed
 Also explore what a “degraded level” really means

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CMOS Transistor
VLSI Design Theory 3
MOS Capacitor
 Gate and body form MOS capacitor
 Operating modes Vg < 0
polysilicon gate
silicon dioxide insulator

 Accumulation +
- p-type body

 Depletion (a)

 Inversion
0 < V g < Vt
depletion region
+
-

(b)

V g > Vt
Example with an NMOS +
inversion region
depletion region
capacitor -

(c)

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CMOS Transistor
VLSI Design Theory 4
Terminal Voltages
Vg
 Mode of operation depends on Vg, Vd, Vs
+ +
Vgs = Vg – Vs Vgs Vgd
- -
 Vgd = Vg – Vd
Vs Vd
 Vds = Vd – Vs = Vgs - Vgd -
Vds +

 Source and drain are symmetric diffusion terminals


 However, Vds  0
 NMOS body is grounded. First assume source may be
grounded or may be at a voltage above ground.
 Three regions of operation
 Cutoff
 Linear
 Saturation

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CMOS Transistor
VLSI Design Theory 5
nMOS Cutoff
 Let us assume Vs = Vb
 No channel, if Vgs = 0
 Ids = 0 Vgs = 0
g
Vgd
+ +
- -
s d

n+ n+

p-type body
b

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CMOS Transistor
VLSI Design Theory 6
NMOS Linear
 Channel forms if Vgs > Vt
Vgs > Vt
 No Currernt if Vds = 0 + g +
Vgd = Vgs

- -
s d
n+ n+ Vds = 0

p-type body
b

 Linear Region:
Vgs > Vt
Vgs > Vgd > Vt
 If Vds > 0, Current flows + g +
- -
from d to s ( e- from s to d) s d
Ids

 Ids increases linearly n+ n+


0 < Vds < Vgs-Vt
with Vds if Vds > Vgs – Vt. p-type body

 Similar to linear resistor b

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CMOS Transistor
VLSI Design Theory 7
NMOS Saturation
 Channel pinches off if Vds > Vgs – Vt.
 Ids “independent” of Vds, i.e., current saturates
 Similar to current source

Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b

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CMOS Transistor
VLSI Design Theory 8
I-V Characteristics
 In Linear region, Ids depends on
 How much charge is in the channel
 How fast is the charge moving

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CMOS Transistor
VLSI Design Theory 9
Channel Charge
 MOS structure looks like parallel plate capacitor while
operating in inversion
 Gate – oxide (dielectric) – channel
 Qchannel =

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

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CMOS Transistor
VLSI Design Theory 10
Channel Charge
 MOS structure looks like parallel plate capacitor while
operating in inversion
 Gate – oxide – channel
 Qchannel = CV
 C=

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

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CMOS Transistor
VLSI Design Theory 11
Channel Charge
 MOS structure looks like parallel plate capacitor while
operating in inversion
 Gate – oxide – channel
 Qchannel = CV
 C = Cg = oxWL/tox = CoxWL Cox = ox / tox
 V = Vgc – Vt = (Vgs – Vds/2) – Vt
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

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CMOS Transistor
VLSI Design Theory 12
Carrier velocity
 Charge is carried by e-
 Carrier velocity v proportional to lateral E-field
between source and drain
 v = mE m called mobility
 E = Vds/L
 Time for carrier to cross channel:
 t=L/v

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CMOS Transistor
VLSI Design Theory 13
NMOS Linear I-V
 Now we know
 How much charge Qchannel is in the channel
 How much time t each carrier takes to cross
Qchannel
I ds 
t
 mCox
W V  V  Vds V
 gs  ds
 2 
t
L
W
 = mCox
  Vgs  Vt  ds Vds
V
L
 2

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CMOS Transistor
VLSI Design Theory 14
NMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
 When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases
current


I ds   Vgs  Vt 
Vdsat V
 dsat
 2 

  Vt 
2
 V gs
2

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CMOS Transistor
VLSI Design Theory 15
NMOS I-V Summary
 Shockley 1st order transistor models (valid for
Large channel devices only)


 0 Vgs  Vt cutoff

  V V V  V
I ds    Vgs  Vt  ds  ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2

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CMOS Transistor
VLSI Design Theory 16
Example
 For a 0.6 mm process (MOSIS site)
From AMI Semiconductor

2.5
 tox = 100 Å Vgs = 5

 m = 350 cm2/V*s
2

 Vt = 0.7 V 1.5 Vgs = 4

Ids (mA)
 Plot Ids vs. Vds 1
Vgs = 3
 Vgs = 0, 1, 2, 3, 4, 5
0.5
 Use W/L = 4/2 l Vgs = 2
Vgs = 1
0
0 1 2 3 4 5
Vds
W  3.9  8.85  1014   W  W
  mCox   350  8    120 m A /V 2
L  100  10  L  L

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CMOS Transistor
VLSI Design Theory 17
PMOS I-V

 All dopings and voltages are inverted for PMOS


 Mobility mp is determined by holes
 Typically 2-3x lower than that of electrons mn
 120 cm2/V*s in AMI 0.6 mm process
 Thus PMOS must be wider to provide same current
 In this class, assume mn / mp = 2

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CMOS Transistor
VLSI Design Theory 18
Capacitance
 Any two conductors separated by an insulator have
capacitance
 Gate to channel capacitor is very important
 Creates channel charge necessary for operation
 Source and drain have capacitance to body
 Across reverse-biased diodes
 Called diffusion capacitance because it is
associated with source/drain diffusion

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CMOS Transistor
VLSI Design Theory 19
Gate Capacitance
 Approximate channel as connected to source
 Cgs = oxWL/tox = CoxWL = CpermicronW
 Cpermicron is typically about 2 fF/mm

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.90)
p-type body

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CMOS Transistor
VLSI Design Theory 20
Diffusion Capacitance
 Csb, Cdb
 Undesirable, called parasitic capacitance
 Capacitance depends on area and perimeter
 Use small diffusion nodes
 Comparable to Cg
for contacted diff
 ½ Cg for uncontacted
 Varies with process

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CMOS Transistor
VLSI Design Theory 21
Pass Transistors
 We have assumed source is grounded
 What if source > 0? VDD
 e.g. pass transistor passing VDD VDD

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CMOS Transistor
VLSI Design Theory 22
NMOS Pass Transistors
 We have assumed source is grounded
 What if source > 0? VDD
 e.g. pass transistor passing VDD
VDD
 Let Vg = VDD
 Now if Vs > VDD-Vt, Vgs < Vt
Vs
 Hence transistor would turn itself off
 NMOS pass transistors pull-up no higher than VDD-Vtn
 Called a degraded “1”
 Approach degraded value slowly (low Ids)
 PMOS pass transistors pull-down no lower than Vtp
 Called a degraded “0”

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CMOS Transistor
VLSI Design Theory 23
Pass Transistor Ckts

VDD VDD VDD


VDD VDD
VDD

VDD

VDD
VSS

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CMOS Transistor
VLSI Design Theory 24
Pass Transistor Ckts

VDD VDD VDD


VDD VDD
VDD
Vs = VDD-Vtn VDD-Vtn
VDD-Vtn VDD-Vtn

VDD
Vs = |Vtp| VDD-Vtn
VDD VDD-2Vtn
VSS

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CMOS Transistor
VLSI Design Theory 25
Effective Resistance
 Shockley models have limited value
Not accurate enough for modern transistors
 Too complicated for much hand analysis
 Simplification: treat transistor as resistor
 Replace Ids(Vds, Vgs) with effective resistance R
 Ids = Vds/R

 R averaged across switching of digital gate


 Too inaccurate to predict current at any given time
 But good enough to predict RC delay

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CMOS Transistor
VLSI Design Theory 26
RC Delay Model
 Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance

 Unit nMOS has resistance R, capacitance C
 Unit pMOS has resistance 2R, capacitance C
 Capacitance proportional to width
 Resistance inversely proportional to width
d
s
kC
kC
R/k
d 2R/k
d
g k g k kC
g k g
s kC kC
kC s
s
d

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CMOS Transistor
VLSI Design Theory 27
RC Values
 Capacitance
 C = Cg = Cs = Cd = 2 fF/mm of gate width
 Values similar across many processes
 Resistance
 R  6 KW*mm in 0.6um process
 Improves with shorter channel lengths
 Unit transistors
 May refer to minimum contacted device (4/2 l)
 Or maybe 1 mm wide device
 Doesn’t matter as long as you are consistent

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CMOS Transistor
VLSI Design Theory 28
Inverter Delay Estimate
 Estimate the delay of a fanout-of-1 inverter

2 Y 2
A
1 1

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CMOS Transistor
VLSI Design Theory 29
Inverter Delay Estimate
 Estimate the delay of a fanout-of-1 inverter
2C

2C
2C
2 Y 2
A Y
1 1
C
R C

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CMOS Transistor
VLSI Design Theory 30
Inverter Delay Estimate
 Estimate the delay of a fanout-of-1 inverter
2C

2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C

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CMOS Transistor
VLSI Design Theory 31
Inverter Delay Estimate
 Estimate the delay of a fanout-of-1 inverter
2C

2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C

d = 6RC
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CMOS Transistor
VLSI Design Theory 32