CMOS Transistor Theory

THANKS TO PROF. DAVID HARRIS

 Outline
 Introduction
 MOS Capacitor
 nMOS I-V Characteristics
 pMOS I-V Characteristics
 Gate and Diffusion Capacitance
 Pass Transistors
 RC Delay Models

CMOS VLSI Design Slide 2

 Introduction
 So far, we have treated transistors as ideal switches
 An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
 Transistor gate, source, drain all have capacitance
– I = C (DV/Dt) -> Dt = (C/I) DV
– Capacitance and current determine speed
 Also explore what a “degraded level” really means

CMOS VLSI Design Slide 3

 MOS Capacitor
 Gate and body form MOS capacitor
 Operating modes Vg < 0
polysilicon gate
silicon dioxide insulator
+
– Accumulation - p-type body

– Depletion (a)

– Inversion 0 < V g < Vt

depletion region
+
-

(b)

V g > Vt
inversion region
+
- depletion region

(c)

CMOS VLSI Design Slide 4

 Terminal Voltages
 Mode of operation depends on Vg, Vd, Vs Vg

– Vgs = Vg – Vs Vgs
+ +
Vgd
– Vgd = Vg – Vd - -

– Vds = Vd – Vs = Vgs - Vgd Vs

-
Vds +
Vd

 Source and drain are symmetric diffusion terminals

– By convention, source is terminal at lower voltage
– Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
– Cutoff
– Linear
– Saturation

CMOS VLSI Design Slide 5

 nMOS Cutoff
 No channel
 Ids = 0

Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b

CMOS VLSI Design Slide 6

 nMOS Linear
 Channel forms
 Current flows from d to s
V > Vt
– e from s to d Vgd = Vgs
gs
- + g +
- -
 Ids increases with Vds s d
Vds = 0
n+ n+
 Similar to linear resistor p-type body
b

Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b

CMOS VLSI Design Slide 7

 nMOS Saturation
 Channel pinches off
 Ids independent of Vds
 We say current saturates
 Similar to current source

Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b

CMOS VLSI Design Slide 8

 I-V Characteristics
 In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?

CMOS VLSI Design Slide 9

 Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
 Qchannel =

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

CMOS VLSI Design Slide 10

 Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
 Qchannel = CV
 C=

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

CMOS VLSI Design Slide 11

 Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
 Qchannel = CV
 C = Cg = oxWL/tox = CoxWL Cox = ox / tox
 V=
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

CMOS VLSI Design Slide 12

 Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
 Qchannel = CV
 C = Cg = oxWL/tox = CoxWL Cox = ox / tox
 V = Vgc – Vt = (Vgs – Vds/2) – Vt
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

CMOS VLSI Design Slide 13

 Carrier velocity
 Charge is carried by e-
 Carrier velocity v proportional to lateral E-field
between source and drain
 v=

CMOS VLSI Design Slide 14

 Carrier velocity
 Charge is carried by e-
 Carrier velocity v proportional to lateral E-field
between source and drain
 v = mE m called mobility
 E=

CMOS VLSI Design Slide 15

 Carrier velocity
 Charge is carried by e-
 Carrier velocity v proportional to lateral E-field
between source and drain
 v = mE m called mobility
 E = Vds/L
 Time for carrier to cross channel:
– t=

CMOS VLSI Design Slide 16

 Carrier velocity
 Charge is carried by e-
 Carrier velocity v proportional to lateral E-field
between source and drain
 v = mE m called mobility
 E = Vds/L
 Time for carrier to cross channel:
– t=L/v

CMOS VLSI Design Slide 17

 nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross

I ds 

CMOS VLSI Design Slide 18

 nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds 
t


CMOS VLSI Design Slide 19

 nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds 
t
 mCox
W V  V  Vds V
 gs  ds
 2 
t
L
W
  Vgs  Vt  ds Vds
V  = mCox
 2 L

CMOS VLSI Design Slide 20

 nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current

I ds 

CMOS VLSI Design Slide 21

 nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current

I ds   Vgs  Vt  dsat Vdsat

V
 2

CMOS VLSI Design Slide 22

 nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current


I ds   Vgs  Vt 
Vdsat V
 dsat
 2 

  Vt 
2
 V gs
2

CMOS VLSI Design Slide 23

 nMOS I-V Summary
 Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds    Vgs  Vt   ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2

CMOS VLSI Design Slide 24

 Example
 We will be using a 0.6 mm process for your project
– From AMI Semiconductor
– tox = 100 Å 2.5
V =5
– m = 350 cm /V*s
gs
2
2
– Vt = 0.7 V 1.5 V =4

Ids (mA)
gs

 Plot Ids vs. Vds 1

– Vgs = 0, 1, 2, 3, 4, 5 0.5
V =3 gs

– Use W/L = 4/2 l

V =2 gs
V =1 gs
0
0 1 2 3 4 5
W  3.9  8.85  1014   W  W Vds
  mCox   350  8    120 m A /V 2
L  100  10  L  L

CMOS VLSI Design Slide 25

 pMOS I-V
 All dopings and voltages are inverted for pMOS
 Mobility mp is determined by holes
– Typically 2-3x lower than that of electrons mn
– 120 cm2/V*s in AMI 0.6 mm process
 Thus pMOS must be wider to provide same current
– In this class, assume mn / mp = 2

– *** plot I-V here

CMOS VLSI Design Slide 26

 Capacitance
 Any two conductors separated by an insulator have
capacitance
 Gate to channel capacitor is very important
– Creates channel charge necessary for operation
 Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is
associated with source/drain diffusion

CMOS VLSI Design Slide 27

 Gate Capacitance
 Approximate channel as connected to source
 Cgs = oxWL/tox = CoxWL = CpermicronW
 Cpermicron is typically about 2 fF/mm

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.90)
p-type body

CMOS VLSI Design Slide 28

 Diffusion Capacitance
 Csb, Cdb
 Undesirable, called parasitic capacitance
 Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg
for contacted diff
– ½ Cg for uncontacted
– Varies with process

CMOS VLSI Design Slide 29