Ben fradj hanene et Halim Kacem

2ING-ISI

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 L’interface série : Définition et Principe
• Permet au MCU de communiquer avec des systèmes à base de
microprocesseur.
• Les données envoyées ou reçues se présentes sous la forme d’une
succession temporelle (sur une seule ligne) de valeurs binaires
images d’un mots.

• Transmission simultanée de 8 bits sur 8 • Données envoyées ou reçues bit par bit (+ lente)
voies différentes (rapide) • données en série pour émission / réception
• fils proches perturbations importantes à (UART registres à décalage)
haut débit • avantage : grande distance, universelle
• pb de place (beaucoup fils) (beaucoup applications)
2  On s’intéresse à ce type de transmission
 L’interface série : Synchrone

La transmission est synchronisée par un signal d’horloge émis par

l’unité maitre

Ben Fradj Hanene 3 06/01/2019

L’interface série: Asynchrone
• pas de signal d’horloge de synchronisation.

• Les unités en liaison possèdent chacune une horloge interne cadencée à la même
fréquence.

• Lorsqu’une unité veut émettre un mot binaire, elle génère un front descendant
sur sa ligne émettrice . A la fin de l’émission de ce mot, la ligne repasse au niveau
haut.

• La donnée à transmettre peut contenir un bit supplémentaire appelé “parité” et

servant à la correction d’erreurs.

Ben Fradj Hanene 4 06/01/2019

Interface série : mode de transmission
 Simplex : Les données circulent dans un seul sens : émetteur vers
récepteur (ex : ordinateur imprimante, souris ordinateur, radio).
 Half duplex : les données circulent dans les 2 sens mais pas
simultanément : la bande passante est utilisée en intégralité (aussi
appelé alternat ou semi-duplex). Exemple : talkie/walkies,
 Full duplex : les données circulent de manière bidirectionnelle et
simultanément : la bande passante est divisée par 2 pour chaque sens
(duplex intégral).

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Les différents interfaces séries
 Plusieurs normes de communication série:
 UART (Universal Asynchronous Recever Transmitter)
 CAN (Controller Area Network)
 SPI (Serial Peripheral Interface)
 I2C (Inter Integrated Circuit)
 USB (Universal serial Bus)
 LIN (Local Interconnect Network)
 Ethernet
 Wireless interfaces
 Zigbee
 bluetooth

Ben Fradj Hanene 6 06/01/2019

Serial interfaces on STM32F4xx
CORTEX-M4 AHB2 (max 168MHz)
D-bus Encryption**
CPU + FPU +
MPU I-bus

Flash I/F
512kB- 1MB Camera Interface
168 MHz

ARM ® 32-bit multi-AHB bus matrix

Flash Memory
S-bus
USB 2.0 OTG FS
128KB SRAM
JTAG/SW Debug External Memory Power Supply
ETM Interface Reg 1.2V

Arbiter (max 150MHz)

POR/PDR/PVD
Nested vect IT Ctrl USB 2.0 OTG
FS/HS XTAL oscillators
1 x Systic Timer 32KHz + 8~25MHz
Ethernet MAC
DMA 10/100, IEEE1588 Int. RC oscillators
16 Channels 32KHz + 16MHz

Bridge APB1 (max 42MHz) PLL

Clock Control AHB1
RTC / AWU
(max 168MHz)
5x 16-bit Timer
51/82/114/140 I/Os
Bridge 4KB backup RAM
2x 32-bit Timer
2x6x 16-bit PWM
Synchronized AC Timer 2x DAC + 2 Timers
2x Watchdog
APB2 (max 84MHz)

(independent & window)

3 x 16bit Timer 2x CAN 2.0B

Up to 16 Ext. ITs 1x SDIO

2 x SPI / I2S
3x 12-bit ADC
1 x SPI 24 channels / 2Msps 4x USART/LIN

2 x USART/LIN Temp Sensor 3x I2C

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9
 Feature
 Architecture
 Registers
 FIFO mode and threshold
 Interrupt s: Transmit and receive
 Hardware flow control
 Software programming

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 UART Protocol (1/2)
 Standard

 Stop bits configuration

0.5 and 1.5 stop bit: To be used when receiving and transmetting data in Smartcard mode.
UART Protocol (2/2)

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USART ON STM32F4
CORTEX-M4 AHB2 (max 168MHz)
D-bus Encryption**
CPU + FPU +
MPU I-bus

Flash I/F
512kB- 1MB Camera Interface
168 MHz

ARM ® 32-bit multi-AHB bus matrix

Flash Memory
S-bus
USB 2.0 OTG FS
128KB SRAM
JTAG/SW Debug External Memory Power Supply
ETM Interface Reg 1.2V

Arbiter (max 150MHz)

POR/PDR/PVD
Nested vect IT Ctrl USB 2.0 OTG
FS/HS XTAL oscillators
1 x Systic Timer 32KHz + 8~25MHz
Ethernet MAC
DMA 10/100, IEEE1588 Int. RC oscillators
16 Channels 32KHz + 16MHz

PLL
USART 2, 3 ,4,5 Clock Control AHB1
Bridge APB1 (max 42MHz)
RTC / AWU
(max 168MHz)
5x 16-bit Timer
51/82/114/140 I/Os
Bridge 4KB backup RAM
2x 32-bit Timer
2x6x 16-bit PWM
Synchronized AC Timer 2x DAC + 2 Timers
2x Watchdog
APB2 (max 84MHz)

(independent & window)

3 x 16bit Timer 2x CAN 2.0B

Up to 16 Ext. ITs 1x SDIO

2 x SPI / I2S
3x 12-bit ADC
1 x SPI 24 channels / 2Msps 4x USART/LIN
USART 1 et 6 2 x USART/LIN Temp Sensor 3x I2C
 USARTS on STM32F4
 6 USARTs
 2 on high speed bus
 4 on low speed bus
 2 DMA channels (for RX et
TX)
 10 interrupts sources
 Irda
(InfraredDataAssociation),
LIN( Local Interconnect
Network), Modem, smart
card support

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 APB1 or APB2

Internal bus (from /to CPU or DMA)

write Read
Transmit Data Register Receive Data Register
8 bits 12 bits

TXE bit=1

TX pin RX pin
Transmit shift register Receive shift register

Génération d’horloge
SClk

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Comment marquer la fin de la
transmission
 Un bit de flag TC (Transfer Complete) est mis à 1 par le hardware dans le Status
Register (SR):
 Si une trame est envoyé et le TXE=1
 pas de nouvelle écriture dans le TDR donc le TC=1

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UART Features (1/3)
 Full duplex, asynchronous communications
 Fully-programmable serial interface characteristics:
 Data can be 8, or 9 bits
 Parity :
 Even (pair), odd (impair), or no-parity bit generation and detection
 MSB bit : The 8th bit when data=8 bits ) or 9 th bit when the data=9)
 stop bit generation : 0,5; 1; 1,5 or 2 (0, 5 and 1,5 for smart card
mode)
UART Features (3/3)
 Programmable baud rate generator
 Integer part mantisse (12 bits)
 Fractional part (4bits)
Up to 2 Mbps

 The receiver implements different user-configurable

oversampling techniques (except in synchronous mode) for data
recovery by discriminating between valid incoming data and
noise.

 The oversampling method can be selected by programming the

OVER8 bit in the USART_CR1 register and can be either 16 or 8
times the baud rate clock .

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USART Registers
 Data registers (32 bits) :
 TDR : contain the data to be transmitted TDR[8…0]
 RDR : contain the received Data
 Configuration registers (32 bits):
 3 USART_CR (Configuration register): to define:
 M bit( word length): 8 or 9 bits
 Number of stop bit,;
 UE bit (UART Enable) to enable UART in CR1
 TE bit(=1) to send an idle frame as first transmission, USART mode (Lin,
Smartcard mode…),
 DMA use or not (DMAR, DMAT) in CR3 …
 USART_BRR register : 12 bits mantissa + 4 bits fractional to define
USARTDIV desired baud rate
 USART_SR register : Status Register
 (TXE, RXNE, TC, …
 TXEIE( TX Empty Interrupt Enable), RXNEIE( RXNE Interrupt Enable) pour
pouvoir générer des interruptions

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Qlq problèmes? Et solution
 Lors de la transmission, le récepteur peut ne pas
pouvoir traiter les données reçues (une donnée non
traitée peut être écraser par la suivante)
  un buffer pour pouvoir stocker un certain nombre de
données avant leur traitement FIFO mode enabled (
not implemented in STM32F4 and available in STM32F7
  contrôle du flow de transmission par le matériel (CTS
et RTS)

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 APB1 or APB2

Internal bus (from /to CPU or DMA)

USART_SendData( USART1, Data[i]) USART_ReceiveData(USART1)
write Read
Transmit data buffer Receiver data buffer
16 × 8 bits 16 × 12 bits

TXE bit=1

TX pin RX pin
Transmit shift register Receive shift register

Génération d’horloge
SClk

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UART Features (2/3)
 16 x 8 bits Tx FIFO (
 16 x 12 bits Rx FIFO (12 bits: 8 Data bits + 4 Error bits : Frame Error,
parity error,Noise Detection, overrun error)
 Configurable Tx and Rx FIFO level
7/8 14 – Bytes
 UART interrupts:
 Receive Interrupt 3/4 12 – Bytes
 Transmit Interrupt 1/2 8 - Bytes
 Receive Timeout Interrupt
1/4 4 - Bytes
 Framing Interrupt
 Parity Error Interrupt 1/8 2 - Bytes

 Break Error Interrupt Disabled 1 - Byte

 Overrun Error Interrupt
 CTS Interrupt

 DMA interface for UART0

 Single Request
 Burst Request
 UART Interrupts : Transmit Interrupt
- Transmit interrupt is generated when the number of empty locations in TX FIFO reaches
the threhold
UART Transmit FIFO: 16 locations

FIFO Levels

FIFO Level 3/4 (12 - Bytes Depth) 7/8 14 - Bytes

Transmit Interrupt
3/4 12 - Bytes

1/2 8 - Bytes

1/4 4 - Bytes

1/8 2 - Bytes

Disabled 1 - Byte

FIFO Disabled (1- Byte Depth)

TXE=1 et si TXEIE=1
Transmit Interrupt

TE ( Transmit Enabile bit=1) written by software ( by USART structure when Tx

mode is choosen)
 UART Interrupts : Receive Interrupt
- RX interrupt is generated when the data containning in RX FIFO reaches the threshold
16 locations UART Receive FIFO

FIFO Levels
7/8 14 - Bytes

3/4 12 - Bytes

1/2 8 - Bytes
FIFO Level 1/2 (8 - Bytes Depth) Receive Interrupt
1/4 4 - Bytes

1/8 2 - Bytes

Disabled 1 - Byte

Receive Interrupt
RXNE=1 et si RXNEEI =1 alors Interrupt

RE ( Receive Enabile bit=1) written by software ( by USART structure when RX mode

is choosen)
Hardware Flow control
 Support hardware flow control :
 CTS : Clear To Send blocks the data transmission at the end of the
current transfer when low
 RTS: Request to Send indicates that the USART is ready to receive a
data (when high)

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Hardware Flow Control :
UART4 send bytes to UART2 Free one location (Read action)

UART4 UART2
Rx Rx

Tx Tx

RTS RTS

CTS CTS

Level: 4 locations depth

UART4 CTS
UART4 Tx FIFO UART2 Rx FIFO
UART2 RTS
UART4 DMA Requests:Transmit Request
Example of an UART4 Transmit DMA Single and Burst request
DMA mode can be enabled for transmit by setting the DMAT bit in USART_CR3 register.
 USART_DMACmd(USART4, USART_DMAReq_Tx, Enable)

DMA
Stream 3

DMA Single Request : the

DMA is requested while
there is one free location in
.
. the transmit FIFo
.

UART0 Transmit FIFO: 16

Memory Level 1/2 : 8 locations
depth

DMA Burst Request : The DMA

locations
is requested when the transmit FIFO
becomes less than the
programmed watermark. The Burst
length depends from the FIFO level.

Tx Burst Length = 8
 UART4 DMA Requests: Receive Request
Example of an UART4 Receive DMA Single and Burst request
DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register.
USART_DMACmd(USARTx, USART_DMAReq_Rx, FunctionalState NewState)

DMA
Stream 2

DMA Single Request :The

UART0 Receive FIFO: 16 locations

. DMA is requested while the
.
. receive FIFO is not empty.
DMA Burst Request : The
DMA is requested when the receive
Memory FIFO becomes greater than the
programmed watermark. The Burst
length depends from the FIFO level.

Level 1/4 : 4 locations depth

Rx Burst Length = 4
 UART1 configuration example
 /* Enable USART1 Clock */ 29
 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE );

 /* set all UART1’s peripheral registers to their reset values */

 USART_DeInit( USART1 ) ;

 USART_InitStructure.USART_BaudRate = 19200;
 USART_InitStructure.USART_WordLength = USART_WordLength_8b;
 USART_InitStructure.USART_StopBits = USART_StopBits_1;
 USART_InitStructure.USART_Parity = USART_Parity_Even;
 USART_InitStructure.USART_HardwareFlowControl=USART_HardwareFlowControl_None;
 USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;

 /* Configure USART1 */
 USART_Init( USART1, &USART_InitStructure);
/* Enable USART1 */
 USART_Cmd( USART1, ENABLE ); , // UART is Now Ready USART 1 is ready now …

 USART_SendData( USART1, Data[i]); // écriture dans TX buffer/register
 tableauR[i]= ReceiveData(USART1); // Read depuis RX buffer/register
Quiz
 What is the maximum UART BaudRate?
____________

 How many levels do the UART FIFOs have?

____________

 What are the different UART DMA requests ?

____________

 What are the two signals needed for Hardware flow control ?
____________
 Receiver ERRORS
 Overrun error
 An "overrun error" occurs when the receiver cannot process the
character that just came in before the next one arrives. Various
devices have different amounts of buffer space to hold received
characters. The CPU must service the UART in order to remove
characters from the input buffer. If the CPU does not service the
UART quickly enough and the buffer becomes full, an Overrun Error
will occur, and incoming characters will be lost.
 Framing error
 A "framing error" occurs when the designated "start" and "stop" bits
are not found. As the "start" bit is used to identify the beginning of an
incoming character, it acts as a reference for the remaining bits. If the
data line is not in the expected state (hi/lo) when the "stop" bit is
expected, a Framing Error will occur.
 Parity error[
 A Parity Error occurs when the parity of the number of 1 bits
disagrees with that specified by the parity bit. Use of a parity bit is
optional, so this error will only occur if parity-checking has been
enabled. 31