Boundary Scan

Boundary scan
• Boundary scan is an integrated method for
testing interconnects on PCB that are
implemented at IC level.
• Inability to test the complex and dense PCBs
using traditional in circuit testers.
• Economic advantage.
• Can test the interconnects between ICs on a
board without using the physical test probes.
 Boundary scan cell
• Can capture the data from pin or core logic
signals, or force data to the pins.
• Captured data is serially shifted out and
compared to the expected results.
• Forced data is serially shifted into the
boundary-scan cells.
• Controlled by scan path or scan chain.
• Eliminates the need for large test vectors
 Boundary scan cell
• Shorter test time.
• Higher test coverage.
• Increased diagnostic capability.
• Lower capital equipment cost.
 Problems in PCBs
• Boards have components on both sides.
• Loss of physical access to fine pitch
components such as SMT
• CPLDs from different vendors, necessitates
different circuit programmers to program
CPLDs.
 Boundary scan
• Boundary scan is cost effective to deal with
these problems.
• Number of devices includes boundary scan
also rises exponentially.
• Boundary scan is an integrated method for
testing interconnects on PCB that are
implemented at IC level.
 Boundary scan
• Joint test action group (JTAG) is the name for
standard test access port and boundary scan
architecture for testing PCBs using boundary scan.
• JTAG is a four/five pin interface added to a chip,
designed so that multiple chips on a board can
have the JTAG lines.
• A test probe need only connect to a single JTAG
port to have access to all chips on a circuit board.
Boundary scan
 Boundary scan
• The connector pins:
• TDI (Test data in)
• TD0 (Test data out)
• TCK (Test clock)
• TMS (Test Mode select)
• TRST (Test Reset)
 Boundary scan
• The protocol is serial like serial peripheral
interface.
• Clk input is at TCK pin.
• Configuration is done by manipulating the
state machine one bit at a time through a TMS
pin.
• One bit of data is transferred in and out per
TCK clock pulse at TDI and TDO pins.
 Boundary scan
• The signals manipulated are between different
functional blocks of the chip.
• Devices communicate to the world via . Set of
input and output pins
• Devices that supports boundary scan have a
shift register cell for each signal pin of the
device.
Boundary scan Register cell
 Boundary scan Register cell
• The primary input and output are
supplemented by a memory element called
boundary-scan cell.
• Boundary scan cell is configured into parallel in
and parallel out shift register.
• Capture- causes the signal values on the device
input pins to be loaded into input cells, and
signal values from internal logic to device
output pins to be loaded into output cells.
 Boundary scan Register cell
• Update operation causes signal values present
in the output scan cell to be passed out
through device output pins.
• Signal values present in the input scan cells
will be passed to the internal logic.
 Boundary scan test applications
• CPLDs, FPGAs, Processors.
• Various types of memory devices.
• Flash memory components