ECE 576 – Power System

Dynamics and Stability

Lecture 13: Exciters, Block Diagrams

Prof. Tom Overbye

Dept. of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
overbye@illinois.edu

1
 Announcements
• Homework 4 is on the website and is due March 6
• Read Chapter 4
• Midterm exam is on March 13 in class
– Closed book, closed notes
– You may bring one 8.5 by 11" note sheet
• You do not have to write down model block diagram or
the synchronous machine differential equations – I'll
supply those if needed
– Simple calculators allowed

2
 IEEE T1 Exciter
• This model was standardized in the 1968 IEEE
Committee Paper with Fig 1 shown below

3
 IEEE T1 Evolution
• This model has been subsequently modified over the
years, called the DC1 in a 1981 IEEE paper (modeled
as the EXDC1 in stability packages)

Note, KE in the
feedback is the
same as
the 1968
approach

Image Source: Fig 3 of "Excitation System Models for Power Stability Studies,"
IEEE Trans. Power App. and Syst., vol. PAS-100, pp. 494-509, February 1981
4
 IEEE T1 Evolution
• In 1992 IEEE Std 421.5-1992 slightly modified it,
calling it the DC1A (modeled as ESDC1A)

VUEL is a
signal
from an
under-
excitation
limiter,
which
we'll
Same model is in 421.5-2005 cover
later
Image Source: Fig 3 of IEEE Std 421.5-1992
5
 Initialization and Coding: Block
Diagram Basics
• To simulate a model represented as a block diagram, the
equations need to be represented as a set of first order
differential equations
• Also the initial state variable and reference values need
to be determined
• Next several slides quickly cover the standard block
diagram elements

6
 Integrator Block

KI
u y
s
• Equation for an integrator with u as an input and y as an
output is
dy
 KI u
dt
• In steady-state with an initial output of y0, the initial
state is y0 and the initial input is zero

7
 First Order Lag Block

K Input
u y Output of Lag Block
1  Ts
• Equation with u as an input and y as an output is
dy 1
  Ku  y 
dt T
• In steady-state with an initial output of y0, the initial
state is y0 and the initial input is y0/K
• Commonly used for measurement delay (e.g., TR block
with IEEE T1)
8
 Derivative Block

KDs
u y
1  sTD
• Block takes the derivative of the input, with scaling KD
and a first order lag with TD
– Physically we can't take the derivative without some lag
• In steady-state the output of the block is zero
• State equations require a more general approach

9
 State Equations for More
Complicated Functions
• There is not a unique way of obtaining state equations
for more complicated functions with a general form
du d mu
0 u  1   m m 
dt dt
dy d n 1 y d n y
0 y  1    n 1 n 1  n
dt dt dt
• To be physically realizable we need n >= m

10
 General Block Diagram Approach
• One integration approach is illustrated in the below
block diagram

Image source: W.L. Brogan, Modern Control Theory,

Prentice Hall, 1991, Figure 3.7 11
 Derivative Example
• Write in form
KD
s
TD
1 TD  s

• Hence 0=0, 1=KD/TD, 0=1/TD

• Define single state variable x, then
dx y Initial value of
 0 u   0 y   x is found by recognizing
dt TD
y is zero so x = -1u
KD
y  x  1u  x  u
TD
12
 Lead-Lag Block

1  sTA input
u y
1  sTB
Output of Lead/Lag

• In exciters such as the EXDC1 the lead-lag block is

used to model time constants inherent in the exciter; the
values are often zero (or equivalently equal)
• In steady-state the input is equal to the output
• To get equations write 1 TA
in form with 0=1/TB, 1=TA/TB, 1  sT s
TB TB
0=1/TB
A

1  sTB 1 TB  s
13
 Lead-Lag Block
• The equations are with
0=1/TB, 1=TA/TB,
0=1/TB
then

dx 1 The steady-state
 0 u   0 y   u  y  requirement
dt TB
that u = y is
TA
y  x  1u  x  u readily apparent
TB

14
 Limits: Windup versus Nonwindup
• When there is integration, how limits are enforced can
have a major impact on simulation results
• Two major flavors: windup and non-windup
• Windup limit for an integrator block
Lmax The value of v is
KI v NOT limited, so
u y its value can
s "windup" beyond
Lmin the limits,
dv If Lmin  v  Lmax then y = v delaying backing
 K I u else If v < L then y = L , off of the limit
dt min min
else if v > Lmax then y = Lmax
15
 Non-Windup Limits Integrator Block
• With non-windup limits, the value of the integral (v
previously) is prevented from exceeding its limit. Thus
it can immediately back off its limits
Lmax dy
 KI u
KI dt
u y (except as indicated below)
s
Lmin dy
If L min  y  L max then normal  KI u
dt
dy
If y  L max then y=L max and if u > 0 then 0
dt
dy
If y  L min then y=L min and if u < 0 then 0
dt
16
 Limits on First Order Lag
• Windup and non-windup limits are handled in a similar
manner for a first order lag
dv 1
 ( Ku  v)
Lmax dt T
K v If Lmin  v  Lmax then y = v
u y
1  sT else If v < Lmin then y = Lmin,
Lmin else if v > Lmax then y = Lmax

Again the value of v is

NOT limited, so its value
can "windup" beyond
the limits, delaying
backing off of the limit
17
 Non-Windup Limit First Order Lag
• With a non-windup limit, the value of y is prevented
from exceeding its limit
dy 1
Lmax   Ku  y 
dt T
K
u y (except as indicated below)
1  sT
Lmin dy 1
If L min  y  L max then normal   Ku  y 
dt T
dy
If y  L max then y=L max and if u > 0 then 0
dt
dy
If y  L min then y=L min and if u < 0 then 0
dt
18
 Lead-Lag Non-Windup Limits
• There is not a unique way to implement non-windup
limits for a lead-lag.
This is the one from
IEEE 421.5-1995
(Figure E.6)

T2 > T1, T1 > 0, T2 > 0

If y > A, then x = A
If y < B, then x = B
If A y  B, then x = y

19
 Ignored States
• When integrating block diagrams often states are
ignored, such as a measurement delay with TR=0
• In this case the differential equations just become
algebraic constraints
• Example: For block at right, K v
Lmax
as T0, v=Ku u y
1  sT
Lmin
• With lead-lag it is quite common for TA=TB, resulting
in the block being ignored

20
 IEEE T1 Example
• Assume previous GENROU case with saturation. Then
add a IEEE T1 exciter with Ka=50, Ta=0.04, Ke=-0.06,
Te=0.6, Vrmax=1.0, Vrmin= -1.0 For saturation assume
Se(2.8) = 0.04, Se(3.73)=0.33
• Saturation function is 0.1621(Efd-2.303)2 (for Efd >
2.303); otherwise zero
• Efd is initially 3.22
• Se(3.22)*Efd=0.437
• (Vr-Se*Efd)/Ke=Efd
• Vr =0.244
• Vref = 2.44/Ka +Vt = 0.0488 + 1.0946=1.1434
21
 IEEE T1 Example
• For 0.1 second fault (from before), plot of Efd and the
terminal voltage is given below
• Initial V4=1.0946, final V4=1.0973
– Steady-state error depends on the value of Ka
Gen Bus 4 #1 Field Voltage (pu) Gen Bus 4 #1 Term . PU

1.1
3.5

3.45 1.05

3.4
1
3.35
Gen Bus 4 #1 Field Voltage (pu)

0.95

Gen Bus 4 #1 Term. PU

3.3

3.25 0.9

3.2
0.85
3.15

3.1 0.8

3.05 0.75

3
0.7
2.95

2.9 0.65

2.85
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10
Time Time

Gen Bus 4 #1 Field Voltage (pu) Gen Bus 4 #1 Term. PU

22
 IEEE T1 Example
• Same case, except with Ka=500 to decrease steady-state
error, no Vr limits; this case is actually unstable
Gen Bus 4 #1 Field Voltage (pu)
Gen Bus 4 #1 Term . PU
12
11
10 1.15
9
8 1.1
7
6 1.05
Gen Bus 4 #1 Field Voltage (pu)

5
1

Gen Bus 4 #1 Term. PU

4
3
2 0.95
1
0 0.9
-1
-2 0.85
-3
-4 0.8
-5
-6 0.75
-7
-8 0.7
-9
0.65
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10
Time 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10
Time
Gen Bus 4 #1 Field Voltage (pu)
Gen Bus 4 #1 Term. PU

23
 IEEE T1 Example
• With Ka=500 and rate feedback, Kf=0.05, Tf=0.5
• Initial V4=1.0946, final V4=1.0957
Gen Bus 4 #1 Field Voltage (pu) Gen Bus 4 #1 Term . PU
8

1.1
7.5

7 1.05

1
Gen Bus 4 #1 Field Voltage (pu)

6.5

Gen Bus 4 #1 Term. PU

6 0.95

5.5 0.9

5 0.85

4.5 0.8

4 0.75

3.5 0.7

3 0.65

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10
Time Time
Gen Bus 4 #1 Field Voltage (pu) Gen Bus 4 #1 Term. PU

24
 WECC Case Type 1 Exciters
• In a recent WECC case with 2782 exciters, 58 are
modeled with the IEEE T1, 257 with the EXDC1 and
none with the ESDC1A
• Graph shows KE value for the EXDC1 exciters in case;
Ke

about 1/3 are separately 1.4

1.3

1.2

excited, and the rest self 1.1

0.9

excited 0.8

0.7

Ke
– Value of KE equal zero
0.6

0.5

0.4

0.3

indicates code should 0.2

0.1

set KE so Vr initializes -0.1

20 40 60 80 100 120 140 160 180 200 220 240

to zero; this is used to mimic Ke

the operator action of trimming this value

25
 DC2 Exciters
• Other dc exciters exist, such as the EXDC2, which is
quite to the EXDC1; about 41 WECC exciters are of
this type
Vr limits are
multiplied by
the terminal
voltage

Image Source: Fig 4 of "Excitation System Models for Power Stability Studies,"
IEEE Trans. Power App. and Syst., vol. PAS-100, pp. 494-509, February 1981
26
 ESDC4B
• Newer dc model introduced in 421.5-2005 in which a
PID controller is added; might represent a retrofit

Image Source: Fig 5-4 of IEEE Std 421.5-2005

27
 Desired Performance
• A discussion of the desired performance of exciters is
contained in IEEE Std. 421.2-1990
• Concerned with
– large signal performance: large, often discrete change in the
voltage such as due to a fault; nonlinearities are significant
• Limits can play a significant role
– small signal performance: small disturbances in which close
to linear behavior can be assumed
• Increasingly exciters have inputs from power system
stabilizers, so performance with these signals is
important
28
 Transient Response
• Figure shows typical transient response performance to
a step change in input

Image Source: IEEE Std 421.2-1990, Figure 3

29
 Small Signal Performance
• Small signal performance can be assessed by either the
time responses, frequency response, or eigenvalue
analysis
• Figure shows the
typical open loop
performance of
an exciter and
machine in
the frequency
domain

Image Source: IEEE Std 421.2-1990, Figure 4

30
 Small Signal Performance
• Figure shows typical closed-loop performance
Peak value of
Mp indicates
relative stability;
too large a value
indicates
overshoot

Note system
connection
is open
We will return to this when we talk about oscillations
Image Source: IEEE Std 421.2-1990, Figure 5
31