Janak H. Patel
Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
jhpatel@illinois.edu
Cost of a Chip
300mm wafer will give 700 ~1cm2 chips
Material Costs (wafer, copper etc) ~5%
Fab amortization cost ($3B/fab) plus
Fab operational cost ~25%
Personnel cost ~20%
Package Cost ~10%
2
Cost of Testing Semiconductor Chips
Three main variable components
Test Application Time
When amortizing the cost of a tester over all chips,
higher test time results in to higher actual cost
Rule of thumb: 1 second per chip!
Tester Pins
Cost of a tester is directly proportional to the number
of pins it supports
3
Example: An IBM chip
7million gates (logic only, RAM not included)
250k Flip-Flops
Full Scan design, all FFs connected as shift
register
Scan Scan
250,000 ffs
in out
7000 Test Vectors
Test Application Time: 7000x250k = 1.75G cycles
at 100MHz scan speed it takes 17.5 Seconds!
at 500MHz scan speed it takes 3.5 Seconds
Tester memory required: 7000x250k = 1.75G bits
Test Responses require additional 1.75G bits 4
Parallel Scan
1000 Parallel Scan Chains by 250 FFs
Scan-in Scan-out
1000 1000
scan-in pins! scan-out pins!
Scan-in
Some Observations
Output Compaction is well established
Number of scan chains is limited by the availability
of pins on a chip and tester scan channels
Additional “pins” on an embedded core require
more routing in the SOC
Parallel Scan has no impact on test data volume
7
Test Vector Compaction
For example, all 40 ISCAS 85 and
ISCAS89 (full scan) circuits, sizes Test Vectors
of the test sets generated by Lower Min
Circuit
Bound Test
MinTest (Hamzaoglu and Patel, ICCAD
C432 27 27
1998, pp. 283-289) meets Lower
C5315 37 37
bounds for 31 out of 40 ISCAS
C7552 65 73
circuits.
S1196 113 113
This shows that Compaction
S1423 20 20
has already reached theoretical
S5378 97 97
lower bounds in many
S38714 62 68
instances
Need solutions beyond vector
compaction
8
BIST: STUMPS Architecture
P. H. Bardell and W. H. McAnney, “Self-Testing of Multichip Logic Modules,”
Proc. Of Int. Test Conf., pp. 200-204, Nov. 1982. (used by IBM for multi-chip-modules)
Scan Chain
LFSR
MISR
Scan Chain
Scan Chain
Scan Chain
Linear Multiple
Feedback Phase
Circuit Under Test Input
Shift Shifter Signature
Register Register
This has the same limitations as any other BIST based scheme
9
Limitations of Logic BIST
BIST is excellent for Data Volume Reduction, But
Lower Fault Coverage. Test Point insertion and/or
additional logic in test generator is required to
cover Random Resistant Faults
Design Modification needed to permit any arbitrary
test pattern
Tri-State logic must be fully decoded
No floating bus is permitted, since unknown values
can corrupt the signature
Switching activities of various modules, and hence
the power, cannot be easily controlled
Will almost always increase the tester time!
Failure Diagnosis becomes extremely difficult
10
Proposed New Method
Illinois Scan Architecture
Applicable to full-scan embedded cores and full-
scan stand-alone chips
Addresses all issues raised earlier –
Low test application time, low pin overhead, and
low test data volume
Does not have any of the limitations of the BIST
No test point insertions and No design
modifications!
Undesirable test vectors can be filtered, e.g.,
Vectors that produce Tri-State Conflicts, Unknown
value generation, or High switching activity
11
Illinois Scan Architecture
MISR
12
Illinois Scan
Internal Scan Chains
Output Compactor
Scan-in
pin
13
Untestable Faults in Illinois Scan
In the figure shown on left,
1
0 all three scan chains will
have identical test vectors
scan in
1
0 Therefore, only applicable
test vectors are 000 and
1
0 111 for the AND gate
Test vectors 110, 011 and
101 cannot be applied due
to Broadcast constraint
This makes three faults on
the AND gate Untestable
Untestable Faults
some of the faults that 800
are testable
600
The number of such
“Additional Untestable 400
Faults” is surprisingly 200
small
0
Experimental Data for
ILS-13207
ILS-15850
ILS-35932
ILS-38417
ILS-38584
Scan Chain divided into 16
chains (arbitrary partition),
with a single scan input.
15
Two Test Modes of Illinois Scan
1. Broadcast Test Mode
2. Serial Test Mode
Scan Chain 1 Scan In
Scan Chain 1
MISR
MISR
Scan Chain 2 Scan Chain 2
Scan In •
• •
• •
•
Scan Chain n
Scan Out
Scan Out Scan Chain n
250
200
150
100
50
0
fs13207
fs15850
fs35932
fs38417
fs38584
ILS-13207
ILS-15850
ILS-35932
ILS-38417
ILS-38584
Circuit
Circuit Versions: fs = full scan, and ILS = Illinois Scan, DIV16
17
Number of Test Cycles
200,000
175,000 scan cycles
150,000 broadcast cycles
125,000
100,000
Cycles
75,000
50,000
25,000
0
fs13207
ILS-13207
fs15850
ILS-15850
fs35932
ILS-35932
fs38417
ILS-38417
fs38584
ILS-38584
Circuit
300,000
Data Bits
250,000
200,000
150,000
100,000
50,000
0
ILS-arb
ILS-arb
ILS-arb
ILS-arb
ILS-arb
fs13207
fs15850
fs35932
fs38417
fs38584
Circuit
Circuit Versions: fs = full scan, and ILS = Illinois Scan, DIV16
19
Illinois Scan
internal scan chains
scan-in
pin
output
compactor
20
Illinois Scan with multiple pins
internal scan chains
external
scan-in
pins
output
compactor
21
IBM Data using Illinois Scan (OPMISR+)
Data and quote From: Test Compression Methods in Cadence Encounter Test Design Edition,
Technology Application Note, December 2003
23
Intel Data on Illinois Scan
From a Paper by D. Wu et. al. of Intel, published in 2003 Int.
Test Conf.
24
More Data on Illinois Scan
7M Gates, 250k flip-flops, 7000 test vectors
Illinois
Scan
26
Illinois Scan with multiple pins
Large Industrial Circuits have used Illinois Scan
with multiple pins
IBM ASIC-4 chip (Design and Test, Sept. 2002, pp. 65-72)
1.14 million gates, 46 pins, 269 internal chains
Intel chips (Int. Test Conf., Sept. 2003, pp. 1229-1238)
ASIC-1, 4 pins, 81 internal chains
27
Optimal Grouping of Chains
scan-in scan chains
pins
Objective:
Minimize number of Scan-In Pins without loss in fault coverage.
28
Compatibility among Chains
Compatibility between two scan cells
Two inputs (scan cells) are compatible if and only if
no fault becomes untestable as a result of tying the
two cells to a single input (Chen&Gupta, ITC 1995)
Compatibility between two scan chains
Two chains are compatible if and only if every pair
of scan-cells that receive the same broadcast
value are compatible (Hamzaoglu&Patel, FTCS 1999)
Determination of all pairwise compatibilities is
computationally very expensive
Resort to an inexpensive algorithm which gives a
subset of all compatible pairs
29
Incompatibilities from a Test Set
A Partially Specified Test Vector, 20-bits long folded on to 5 chains
Vector 1 Chain
001x 0xx1 x01x 0011 xx11 0 0 1 x a
0 x x 1 b
No conflicting values found
x 0 1 x c
0 0 1 1 d
x x 1 1 e
Vector 2
001x 0xx1 x11x 0011 xx11 0 0 1 x a
Chains a and c are incompatible,
0 x x 1 b
so are chains c and d x 1 1 x c
0 0 1 1 d
x x 1 1 e
30
Example of Chain Grouping
Given Incompatible Pairs:
AB, AD, AG, BD, BE, BF, CE, CF, EF, EG, EH, FH
Construct a Graph with Nodes=Chains and Edges=Incompatibility
A B C A
B
C
D E F D
E
F
G H G
H
31
Dual-mode Illinois Scan
A A
B B
C C
D D
E E
F F
G G
H H
32
Dual Mode for Pin Reduction
no. of no. of Reduction
Circuit
Chains Pins Factor
64 8 8.0
s13207.1
107 9 11.8
54 7 7.7
s15850.1
89 11 8.0
52 5 10.4
s38417
82 7 11.7
90 7 12.8
s38584.1
119 8 14.8
33
Illinois Scan: Summary
A simple DFT technique, ideal for reducing test
costs for large chips
Significant reduction in test application time, test
data and test pins without loss in fault coverage
Even a “dumb” partition is very effective!
For large chips, 400 factor reduction is likely!
34
More information on Illinois Scan
1. I. Hamzaoglu and J.H. Patel, “Reducing test application time for full-scan
embedded cores,” Proc. 29th Int. Symp. On Fault-Tolerant Computing
(FTCS-29), pp.260-267, June 1999
2. F. Hsu, K. Butler and J.H. Patel, “A case study on the implementation of
Illinois Scan Architecture,” Proc. Int. Test Conf. pp. 538-547, October 2001
3. A.R. Pandey and J.H. Patel, “An incremental algorithm for test generation
in Illinois Scan Architecture based designs,” Proc. Of Design Automation and
Test in Europe (DATE), pp. 368-375, March 2002.
4. A.R. Pandey and J.H. Patel, “Reconfiguration techniques for reducing test
time and test data volume in Illinois Scan Architecture based designs,” IEEE
VLSI Test Symp. (VTS), pp. 9-15, April 2002.
5. M.A. Shah and J.H. Patel, “Enhancement of the Illinois Scan Architecture
for Use with Multiple Scan Inputs,” IEEE Computer Society Annual
Symposium on VLSI, pp. 167-172, Feb. 2004. 35