The Big Picture: The Performance Perspective

° Performance of a machine is determined by: CPI

• Instruction count
• Clock cycle time
• Clock cycles per instruction
Inst. Count Cycle Time
° Processor design (datapath and control) will
determine:
• Clock cycle time
• Clock cycles per instruction

° Today:
• Single cycle processor:
- Advantage: One clock cycle per instruction
- Disadvantage: long cycle time CS152
Lec8.1
 How to Design a Processor: step-by-
step
° 1. Analyze instruction set => datapath requirements
• the meaning of each instruction is given by the register transfers
• datapath must include storage element for ISA registers
- possibly more
• datapath must support each register transfer

° 2. Select set of datapath components and establish clocking

methodology

° 3. Assemble datapath meeting the requirements

° 4. Analyze implementation of each instruction to determine setting of

control points that effects the register transfer.

° 5. Assemble the control logic

CS152
Lec8.2
 The MIPS Instruction
Formats
° All MIPS instructions are 32 bits long. The three instruction formats:
31 26 21 16 11 6 0
• R-type op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
31 26 21 16 0
• I-type op rs rt immediate
6 bits 5 bits 5 bits 16 bits
31 26 0
• J-type
op target address
6 bits 26 bits

° The different fields are:

• op: operation of the instruction
• rs, rt, rd: the source and destination register specifiers
• shamt: shift amount
• funct: selects the variant of the operation in the “op” field
• address / immediate: address offset or immediate value
• target address: target address of the jump instruction CS152
Lec8.3
 Step 1a: The MIPS-lite Subset for
today
31 26 21 16 11 6 0
° ADD and SUB
op rs rt rd shamt funct
• addU rd, rs, rt
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
• subU rd, rs, rt
31 26 21 16 0
° OR Immediate:
op rs rt immediate
• ori rt, rs, imm16 6 bits 5 bits 5 bits 16 bits
31 26 21 16 0
° LOAD and STORE Word op rs rt immediate
• lw rt, rs, imm16 6 bits 5 bits 5 bits 16 bits
• sw rt, rs, imm16
31 26 21 16 0
° BRANCH: op rs rt immediate
• beq rs, rt, imm16 6 bits 5 bits 5 bits 16 bits

CS152
Lec8.4
 Logical Register Transfers
° RTL gives the meaning of the instructions
° All start by fetching the instruction
op | rs | rt | rd | shamt | funct = MEM[ PC ]
op | rs | rt | Imm16 = MEM[ PC ]

inst Register Transfers

ADDU R[rd] <– R[rs] + R[rt]; PC <– PC + 4
SUBU R[rd] <– R[rs] – R[rt]; PC <– PC + 4
ORi R[rt] <– R[rs] | zero_ext(Imm16); PC <– PC + 4
LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4
STORE MEM[ R[rs] + sign_ext(Imm16) ] <– R[rt]; PC <– PC + 4
BEQ if ( R[rs] == R[rt] ) then PC <– PC + 4 +
sign_ext(Imm16)] || 00
else PC <– PC + 4
CS152
Lec8.5
 Step 1: Requirements of the Instruction
Set
° Memory
• instruction & data
° Registers (32 x 32)
• read RS
• read RT
• Write RT or RD
° PC
° Extender
° Add and Sub register or extended immediate
° Add 4 or extended immediate to PC
CS152
Lec8.6
 Step 2: Components of the
Datapath

° Combinational Elements

° Storage Elements
• Clocking methodology

CS152
Lec8.7
 Combinational Logic Elements (Basic Building
Blocks) CarryIn
° Adder A
32

Adder
Sum
32
B Carry
32

Select
° MUX
A
32
MUX

Y
32
B
32
OP

° ALU A
32
ALU

Result
32
B
32 CS152
Lec8.8
 Storage Element: Register (Basic Building
Block)
° Register Write Enable
• Similar to the D Flip Flop except
Data In Data Out
- N-bit input and output
N N
- Write Enable input
• Write Enable:
Clk
- negated (0): Data Out will not
change
- asserted (1): Data Out will
become Data In

CS152
Lec8.9
 Storage Element: Register
File
° Register File consists of 32 registers: RWRA RB
• Two 32-bit output busses: Write Enable 5 5 5
busA and busB busA
• One 32-bit input bus: busW busW 32 32-bit 32
32 Registers busB
° Register is selected by: Clk
32
• RA (number) selects the register to put on busA (data)
• RB (number) selects the register to put on busB (data)
• RW (number) selects the register to be written
via busW (data) when Write Enable is 1

° Clock input (CLK)

• The CLK input is a factor ONLY during write operation
• During read operation, behaves as a combinational logic
block:
- RA or RB valid => busA or busB valid after “access
time.” CS152
Lec8.10
 Storage Element: Idealized
Memory
Write Enable Address
° Memory (idealized)
• One input bus: Data In
Data In DataOut
• One output bus: Data Out 32 32
Clk
° Memory word is selected by:
• Address selects the word to put on Data Out
• Write Enable = 1: address selects the memory
word to be written via the Data In bus

° Clock input (CLK)

• The CLK input is a factor ONLY during write operation
• During read operation, behaves as a combinational logic
block:
- Address valid => Data Out valid after “access time.”

CS152
Lec8.11
 Clocking
Methodology
Clk
Setup Hold Setup Hold
Don’t Care

. . . .
. . . .
. . . .

° All storage elements are clocked by the same clock edge

° Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew

° (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time

CS152
Lec8.12
 Step 3: Assemble DataPath meeting our
requirements
° Register Transfer Requirements
 Datapath Assembly

° Instruction Fetch

° Read Operands and Execute Operation

CS152
Lec8.13
 3a: Overview of the Instruction Fetch
Unit
° The common RTL operations
• Fetch the Instruction: mem[PC]
• Update the program counter:
- Sequential Code: PC <- PC + 4
- Branch and Jump: PC <- “something else”

Clk PC

Next Address
Logic

Address
Instruction Word
Instruction
Memory 32

CS152
Lec8.14
 3b: Add &
Subtract
° R[rd] <- R[rs] op R[rt] Example: addU rd, rs, rt
• Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields
• ALUctr and RegWr: control logic after decoding the
instruction
31 26 21 16 11 6 0
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

Rd Rs Rt
RegWr ALUctr
5 5 5
busA
Rw Ra Rb
busW 32 Result

ALU
32 32-bit
32 32
Registers
Clk busB
32

CS152
Lec8.15
 Register-Register Timing: One complete
Clk
cycle
Clk-to-Q
PC Old Value New Value
Instruction Memory Access Time
Rs, Rt, Rd, Old Value New Value
Op, Func
Delay through Control Logic
ALUctr Old Value New Value

RegWr Old Value New Value

Register File Access Time
busA, B Old Value New Value
ALU Delay
busW Old Value New Value

Rd Rs Rt
RegWr 5 5 ALUctr Register Write
5
Occurs Here
busA
Rw Ra Rb
busW 32 Result

ALU
32 32-bit
32 Registers 32
Clk busB
32
CS152
Lec8.16
 3c: Logical Operations with
°
Immediate
R[rt] <- R[rs] op ZeroExt[imm16] ]
31 26 21 16 11 0
op rs rt immediate
6 bits 5 bits 5 bits rd? 16 bits
31 16 15 0
0000000000000000 immediate
16 bits 16 bits
Rd Rt
RegDst
Mux
Rs Rt? ALUctr
RegWr 5 5 5
busA
Rw Ra Rb
busW 32 Result
32 32-bit

ALU
32 Registers 32
Clk busB
32
Mux
ZeroExt

imm16
16 32
ALUSrc
CS152
Lec8.17
 3d: Load
°
Operations
R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16

31 26 21 16 11 0
op rs rt immediate
6 bits 5 bits 5 bits rd 16 bits

Rd Rt
RegDst
Mux
Rs Rt?
RegWr 5 ALUctr
5 5
busA W_Src
Rw Ra Rb
busW 32
32 32-bit

ALU
32 Registers 32
Clk busB MemWr

Mux
32
Mux

WrEn Adr
Extender

Data In 32
32 ?? Data
imm16 32
16 Memory
Clk
ALUSrc
CS152
ExtOp Lec8.18
 3e: Store
Operations
° Mem[ R[rs] + SignExt[imm16] <- R[rt] ] Example: sw rt, rs, imm16
31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits
Rd Rt ALUctr MemWr W_Src
RegDst
Mux
Rs Rt
RegWr 5 5 5
busA
Rw Ra Rb
busW 32
32 32-bit

ALU
32 Registers 32
Clk busB

Mux
Mux
32
WrEn Adr
Extender

Data In 32 32
imm16 Data
32
16 Memory
Clk

ExtOp ALUSrc
CS152
Lec8.19
 3f: The Branch
Instruction
31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits

° beq rs, rt, imm16

• mem[PC] Fetch the instruction from memory

• Equal <- R[rs] == R[rt] Calculate the branch condition

• if (Equal) Calculate the next instruction’s address

- PC <- PC + 4 + ( SignExt(imm16) x 4 )
• else
- PC <- PC + 4

CS152
Lec8.20
 Datapath for Branch
Operations
° beq rs, rt, imm16 Datapath generates condition (equal)

31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits
Inst Address Cond

nPC_sel Rs Rt
4 RegWr 5 5 5
Adder

32 busA
Rw Ra Rb
00

busW

Equal?
32 32-bit 32
Mux

Registers
PC

Clk busB
32
Adder
PC Ext

imm16
Clk

CS152
Lec8.21
 Putting it All Together: A Single Cycle
Datapath
Instruction<31:0>

<21:25>

<16:20>

<11:15>
Inst

<0:15>
Memory
Adr
Rs Rt Rd Imm16

nPC_sel RegDst ALUctr MemWr MemtoReg

Equal
Rd Rt
1 0
Rs Rt
4 RegWr 5 5 5
Adder

busA
busW Rw Ra Rb =
00

32 32-bit 32

ALU
Mux

32 Registers busB 32 0
PC

Mux
32

Mux
Adder

Clk 32 WrEn Adr 1

Extender

1 Data In
PC Ext

imm16 32 Data
Clk
imm16

16 Memory
Clk

ExtOp ALUSrc CS152

Lec8.22
 An Abstract View of the Critical
° Path file and ideal memory:
Register
• The CLK input is a factor ONLY during write operation
• During read operation, behave as combinational logic:
- Address valid => Output valid after “access time.”
Critical Path (Load Operation) =
PC’s Clk-to-Q +
Ideal Instruction Memory’s Access Time +
Instruction Register File’s Access Time +
Instruction ALU to Perform a 32-bit Add +
Memory
Rd Rs Rt Imm Data Memory Access Time +
5 5 5 16 Setup Time for Register File Write +
Instruction Clock Skew
Address
A Data
Rw Ra Rb 32
Next Address

32 Address
32 Ideal
32 32-bit
ALU
Data
PC

Registers Data In
B Memory

Clk Clk
32
Clk

CS152
Lec8.23
 An Abstract View of the
Implementation

Ideal Control
Instruction Control Signals Conditions
Instruction
Memory
Rd Rs Rt
5 5 5
Instruction
Address
A Data
Rw Ra Rb 32 Data
Next Address

32 Address
32 Ideal Out
32 32-bit

ALU
Data
PC

Registers Data In Memory

B

Clk Clk
32
Clk

Datapath

CS152
Lec8.24
Steps 4 & 5: Implement the
control

Next time

CS152
Lec8.25
 Summary
° 5 steps to design a processor
• 1. Analyze instruction set => datapath requirements
• 2. Select set of datapath components & establish clock methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to determine setting of
control points that effects the register transfer.
• 5. Assemble the control logic

° MIPS makes it easier

• Instructions same size
• Source registers always in same place
• Immediates same size, location
• Operations always on registers/immediates

° Single cycle datapath => CPI=1, CCT => long

° Next time: implementing control
CS152
Lec8.26