DESIGN OF LOW POWER AND AREA

USING HYBRID FULL - ADDER

SUPERVISOR PRESENTED-BY

Mr. M. Rajmohan, M.Tech, (Ph.D.) Salam Surjit Singh

Assistant Professor (S.G) (16236002) M.Tech VLSI & ES

ECE Department ECE Department

HITS HITS
 OBJECTIVE

The main objective of the project is to design Hybrid Full

Adder using Transmission Gate (TG) and Pass Transistor Logic
(PTL) for improving the performance of Full Adder in terms of
power and area.
 INTRODUCTION

 Full Adder is the basic fundamental building block of most of the

computing system where arithmetic operation take place.

 Full adders can be implemented using different logic style :

 Complementary MOSFET (CMOS).
 Pass Transistor Logic (PTL).
 Complementary Pass Transistor Logic (CPL).
 Transmission Function (TFA).
 Transmission Gate (TGA).
 Hybrid pass logic with static CMOS (HPSC).
 CHARACTERISTICS OF TG

• Realize complex logic function using a small number of

complementary transistors.
• It solve the problem of low logic level swing by using PMOS as
well as NMOS.
• The advantage of the transmission gate is simplicity. The
transmission gate can implement certain structures with less
transistors which saves the area.
 CHARACTERISTICS OF PTL

• High speed due to the small node capacitance.

• It reduces the count of transistors which is used to make different
logic gates, by eliminating redundant transistors tends to low power
dissipation which gives less area so low interconnection effects.

• Threshold drop across the single-channel pass-transistor results in

reduced current drive and hence slower operation at reduced supply
voltages.
• PMOS device in the inverter is nor fully turned off and hence direct
path static power dissipation could be significant.
 BLOCK DIAGRAM OF FULL ADDER

Fig: Full Adder

 Module 1 take input A and B

 Module 2 gives Sum Output
 Module 3 gives Carry output
 LITERATURE SURVEY

[1] “One-bit Full Adder Using 0.25μm CMOS Technology” G. Vinutna

Ujwala, K. Babulu Proceedings of AECE-IRAJ International Conference,
14th July 2013.

 This paper gives out the design of Full adder implementation using
CMOS technology i.e. PMOS and NMOS transistors (28T).

 The main advantage of this design is robustness against voltage scaling

and transistor sizing.

 The main disadvantages is because of more number of transistor the input

capacitance is high and requirement of buffer unit hence, the area and
noise increased.
 Cont.…

[2] “Low-power High-speed Hybrid 1-bit Full Adder” Circuit Partha

Bhattacharyya, Senior, Bijoy Kundu, Sovan Ghosh, Vinay Kumar, and Anup
Dandapat, IEEE Transactions on Very Large-Scale Integration (VLSI)
Systems, Vol. 23, No. 10, OCTOBER 2015.

 This Proposed paper design is based on implementation of Full adder

using Hybrid style by combining CMOS and Transmission Gate (TG). The
main objective of this paper is to improve the power and delay.
 Cont.…
[3] “Design and Analysis of One Bit Hybrid Full Adder Using Pass Transistor
Logic” Rakesh Chowdary Gutta1, UhaNikitha Rachapalli2, Piyusha
Remala3, Phaneendra vale4, T V Rama Krishna International Journal of Pure
and Applied Mathematics Volume 116 No. 5 2017, 169-174.

 In this project full-adder is implemented using 12T hybrid design style by

using CMOS with Pass transistor logic (PTL). Here EX-NOR module in
the full adder is implemented using 2T pass transistors logic which give
less power consumption by reducing number of transistors.

 This design gives out low power and less area.

 The main disadvantages is threshold drop across the channel of Pass

transistor result in reduced current drive hence slower operation.
 Performance analysis of the existing Full Adder using 90nm
technology based on reference [2] paper:
Reference Design Average Delays Transistor
[2] Power (µW) (ns) Count
TGA 1.762 0.231 20
Low-power
High-speed TFA 1.736 0.319 16
Hybrid 1-bit
Full Adder CMOS & 1.176 0.091 16
TG
 Hybrid style using CMOS and TG is having less power as
compare to other design style and also reduce transistor count.

 TGA is having more number of transistor.

 In TFA transistor count is reduce but speed is less.

LOGIC DIAGRAM OF 1-BIT FULL ADDER
USING TRANSMISSION GATE ADDER
(TGA)
S-EDIT DESIGN OF FULL ADDER USING
(TRANSMISSION GATES )
WAVEFORM OUTPUT FOR TGA
 PROPOSED METHOD

 Hybrid Configuration for efficient low power by Combining TG and

Pass Transistor Logic.
 Which give less power consumption.
 Moderate number of transistor.
 TRANSMISSION GATE (TG)

 Transmission gate logic used complementary transistors. It sove the

problem of low level swing by using PMOS as well NMOS.
 PROPOSED 2T-XOR PTL LOGICS

 Low power dissipation as a result of reduced in number of transistor.

LOGIC DIAGRAM OF 1-BIT FULL ADDER
USING TG AND PTL
 S-EDIT DESIGN OF
FULL ADDER USING TG AND PTL
WAVEFORM OUTPUT FOR HYBRID TG
AND PTL
PERFORMANCE ANALYSIS OF THE FULL
ADDER USING 250nm TECHNOLOGY :

Design Average Power Delay Transistor Details

Watts Count

TGA 0.093 µ_watt 40.008n 20 Existing

TFA 0.048 µ_watt 0.147n 16 Existing

CMOS&TG 0.072 µ_watt 0.145n 16 Existing

(6TXOR)
PMOS&TG 0.007 µ_watt 20.070n 12 Proposed
(2TXOR) Method
L-EDIT DESIGN FOR FULL ADDER
 REFERENCES

[1] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A

Design Perspective, 2nd ed. Delhi, India: Pearson Education, 2003.
[2] Partha Bhattacharyya, BijoyKundu, Sovan Ghosh, Vinay Kumar, AnupDandapat,”
Performance Analysis of a Low-Power High- Speed Hybrid 1-bit Full Adder Circuit”,
IEEE Transactions On Very Large Scale Integration (VLSI) SYSTEMS, VOL. 23,
NO. 10, OCTOBER 2015.
[3] K. Navi, M. Maeen, V. Foroutan, S. Timarchi, and O. Kavehei, “A novel
low-power full-adder cell for low voltage,” VLSI J. Integr., vol. 42, no. 4,
pp. 457–467, Sep. 2009.
[4] D. Radhakrishnan, “Low-voltage low-power CMOS full adder,” IEE Proc.-
Circuits Devices Syst., vol. 148, no. 1, pp. 19–24, Feb. 2001.
[5] R. Zimmermann and W. Fichtner, “Low-power logic styles: CMOS versus pass-
transistor logic,” IEEE J. Solid-State Circuits, vol. 32, no. 7,pp. 1079–1090, Jul. 1997.
 REFERENCES

[6] C. H. Chang, J. M. Gu, and M. Zhang, “A review of 0.18-μm full adder

performances for tree structured arithmetic circuits,” IEEE Trans. Very Large Scale
Integr. (VLSI) Syst., vol. 13, no. 6, pp. 686–695, Jun. 2005.
[7] A. M. Shams, T. K. Darwish, and M. A. Bayoumi, “Performance analysis
of low-power 1-bit CMOS full adder cells,” IEEE Trans. Very Large
Scale Integr. (VLSI) Syst., vol. 10, no. 1, pp. 20–29, Feb. 2002.
[8] M. Zhang, J. Gu, and C.-H. Chang, “A novel hybrid pass logic with static CMOS
output drive full-adder cell,” in Proc. Int. Symp. Circuits Syst., May 2003, pp. 317–320.