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Memory & Storage

Memory Functionality
Source for DX4100 Picture
Dana Angluin
Source for Computer Architecture Overview Picture Benchmark Graphics
Digital Life
Pictures of CPU Overview, Single Bus Architecture, Tripe Bus Architecture
Roy M. Wnek Virginia Tech. CS5515 Lecture 5
Chipset and Socket Information
Historical Data and Pictures
The Computer Museum History Center.
Amd Processor Pictures
Toms hardware
Intel Motherboard Diagram/Pentium 4 Picture
Intel Corporation
GPU Info
The Abacus
Abacus-Online-Museum 4th Wave Inc.
NV20 Design Pictures
Information Also from Digital Life
Clint Fleri
Main Memory
Memory Hierarchy

•DRAM is short for Dynamic Random Access Memory

•SRAM is short for Static Random Access Memory

DRAM is dynamic in that, unlike SRAM, it needs to have

its storage cells refreshed or given a new electronic charge
every few milliseconds. SRAM does not need refreshing
because it operates on the principle of moving current that
is switched in one of two directions rather than a storage cell
that holds a charge in place.
Parity vs. Non-Parity

Parity is error detection that was developed to

notify the user of any data errors. By adding a
single bit to each byte of data, this bit is
responsible for checking the integrity of the
other 8 bits while the byte is moved or stored.
Since memory errors are so rare, many of
today’s memory is non-parity.

SIMM-Single In-line Memory Module

DIMM-Dual In-line Memory Modules
RIMM-Rambus In-line Memory Modules
SIMMs offer a 32-bit data path while DIMMs offer a
64-bit data path. SIMMs have to be used in pairs on
Pentiums and more recent processors
RIMM is the one of the latest designs. Because of
the fast data transfer rate of these modules, a heat
spreader (aluminum plate covering) is used for each
Evolution of Memory

1970 RAM / DRAM 4.77 MHz

1987 FPM 20 MHz
1995 EDO 20 MHz
1997 PC66 SDRAM 66 MHz
1998 PC100 SDRAM 100 MHz
1999 RDRAM 800 MHz
1999/2000 PC133 SDRAM 133 MHz
2000 DDR SDRAM 266 MHz
2001 EDRAM 450MHz
• FPM-Fast Page Mode DRAM
-traditional DRAM

•EDO-Extended Data Output

-increases the Read cycle between Memory and the CPU

•SDRAM-Synchronous DRAM
-synchronizes itself with the CPU bus and runs at higher
clock speeds
-DRAM with a very high bandwidth (1.6 GBps)

•EDRAM-Enhanced DRAM
-(dynamic or power-refreshed RAM) that includes a
small amount of static RAM (SRAM) inside a larger
amount of DRAM so that many memory accesses will
be to the faster SRAM. EDRAM is sometimes used as
L1 and L2 memory and, together with Enhanced
Synchronous Dynamic DRAM, is known as cached
Read Operation
•On a read the CPU will first try to find the data in the cache, if it is not
there the cache will get updated from the main memory and then return
the data to the CPU.
Write Operation

• On a write the CPU will write the information into

the cache and the main memory.