 The bus is the mechanism by which the CPU

communicates with memory and devices.

 A bus is, at a minimum, a collection of wires,
but the bus also defines a protocol by which
the CPU, memory and devices communicate.
 One of the major role of the bus is to
provide an interface to memory.

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Hardware Architecture of computing
platform

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 Bus protocol determines how devices
communicate.
 Devices on the bus go through sequences of
states.
 Protocols are specified by state machines, one
state machine per actor in the protocol.
 May contain asynchronous logic behavior.

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1. Device1 raises its o/p to signal an enquiry,
which tells device2 that it should get ready to
listen for data.
2. When device2 is ready to receive, it raises
its o/p to signal an acknowledgement. At this
point, device1 and 2 can transmit or receive.
3. Once the data transfer is complete, device2
lowers its o/p, signaling that it has received
the data.
4. After seeing that ack has been released,
device1 lowers its o/p.
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 device 1
enq
device 1 device 2

ack
device 2

1 2 3 4

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 Clock provides synchronization to the bus
components,
 R/W’ is true when the bus is reading and false
when the bus is writing,
 Address is an a bit bundle of signals that
transmits the address for an access,
 Data is an n bit bundle of signals that can carry
data to or from the CPU,
 Data ready’ signals when the values on the data
bundle are valid

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 A timing diagram shows how the signals on a
bus vary over time,
 since values like the address and data can take
on many values, some standard notation is
used to describe signals.
 A signal can go between 0/1 state and a
stable/changing state.
 To be sure that signals go to their proper values
at the proper time, timing diagram sometimes
show timing constraints.
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 Timing diagram shown with timing constraints
for the example bus.
 The diagram shows a read and a write.
 Timing constraints shown only for read
operation, but similar constraints applies to
the write operation.
 The bus is normally in read mode, since that
does not change any state.
 During a read the external device or memory is
sending a value on the data lines, while during
a write the CPU is controlling the data lines.
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 A read or write is initiated by setting address enable high
after the clock starts to rise. We set R/W’=1 to indicate a
read and the address lines are set to the desired address.
 One clock cycle later, the memory or device is expected to
assert the data value at that address on the data lines.
simultaneously, the external device specifies that the data
are valid by pulling down the data ready’ line. This line is
active low, meaning that a logically true value is indicated
by a low voltage, in order to provide increased immunity to
electrical noise.
 The CPU is free to remove the address at the end of clock
cycle and must do so before the beginning of the next cycle.
The external device has a similar requirement for removing
the data value from the data lines.
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 The handshake that tells the CPU and devices
when data are to be transferred is formed by
data ready for the acknowledge side, but Is
implicit for the inquiry side.
 The data ready signal allows the bus to be
connected to devices that are slower than bus.
 The cycle between the minimum time at which
data can be asserted and when it is actually
inserted are known as wait states.
 In this burst read transaction the CPU sends
one address but receives of data values.
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14
Get Done Sendda Release
data ta ack

See ack Ack

Adrs Adrs

Wait Wait

device
CPU start

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 The state machine view of the bus transaction
is also helpful and useful complement to the
timing diagram.
 It shows the transition of control signal.
 And the CPU decides to perform a read
transaction, it moves to a new state, sending
bus signals that cause the device to behave
appropriately.
 The device’s state transition graph captures it
side of the protocol.
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 Direct memory access
(DMA) performs data
transfers without
executing instructions.
 CPU sets up transfer.
 DMA engine
fetches, writes.
 DMA controller is a
separate unit.

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 By default, CPU is bus master and initiates
transfers.
 DMA must become bus master to perform
its work.
 CPU can’t use bus while DMA operates.
 Bus mastership protocol:
 Bus request.
 Bus grant.

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 CPU sets DMA registers for
start address, length.
 DMA status register
controls the unit.
 Once DMA is bus master, it
transfers automatically.
 May run continuously until
complete.
 May use every n th bus cycle.

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 Multiple busses allow
parallelism:
CPU slow device
 Slow devices on one
bus.

bridge
 Fast devices on memory
slow device
separate bus.
 A bridge connects two high-speed
busses. device

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 Two varieties:
 AHB is high-performance.
 APB is lower-speed, lower
cost.
 AHB supports
pipelining, burst
transfers, split
transactions, multiple bus
masters.
 All devices are slaves on
APB.

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 Several different types of memory:
 Read Only Memories
 Flash.
 Read/Write Memories
 DRAM.
 SRAM.

 Each type of memory comes in varying:

 Capacities.
 Widths.

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 Dynamic RAM is dense, requires refresh.
 Synchronous DRAM is dominant type.
 SDRAM uses clock to improve performance,
pipeline memory accesses.
 Static RAM is faster, less dense, consumes
more power.

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 ROM may be programmed at factory.
 Flash is dominant form of field-
programmable ROM.
 Electrically erasable, must be block erased.
 Random access, but write/erase is much slower

than read.

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 Non-volatile memory.
 Flash can be programmed in-circuit.
 Random access for read.

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 Write is much slower than read.
 1.6 s write, 70 ns read.
 Blocks are large (approx. 1 Mb).
Modern lifetime approx. 1 million writes.

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