ARM

 Established as Advanced RISC Machines Ltd. In 1990 as a UK

based joint venture between Apple Computer, Acorn Computer
Group and VLSI Technology
 Apple and VLSI provided funding
 Acorn supplied technology and first 12 engineers
 Introduction of ARM6 – TM family in 1991, VLSI initial licensee
 In April 1998 listed on the London Stock Exchange and Nasdaq
 ARM

 Develops the ARM range of RISC processor cores

 Licenses its RISC microprocessor core and SoC IP to a network of
partners; Semiconductor and system companies
 ARM does not manufacture silicon itself
 Also licenses architectural extensions, development tools,
peripheral IP and SoC solutions
1. ARM – The Company

2. Instruction Set

3. ARM7TDMI-S

4. Systems

5. Other ARM cores

6. NXP Implementation

7. Q & A
 ARM Architecture
Bus Width
 ARM7 is a 32-bit architecture
 Data paths and (ARM)
instructions are 32 bits wide
 Von Neumann architecture
• instructions and data use the
same 32 – bit data bus
 There is a subset of 16-bit
instructions (Thumb) optimized
for code density
 Thumb State
 Set of Instructions re-coded into 16 bits
 Improved code density by  30%
 Saving program memory space
 In Thumb state only the program code is 16 – bit wide
 After fetching the 16-bit instructions from memory, they are
de-compressed to 32 bit instructions before they are decoded
and executed
 All operations are still 32 – bit operations
 Data Types and Alignment
 Definitions (Little endian or big endian are options):
• Word = 32 bits (four bytes)
• Halfword = 16 bits (two bytes)
• Byte = 8 bits
 Processor Modes
ARM7 has seven operating modes
1. User Unprivileged mode under which most applications run
2. FIQ entered, when a high priority (fast) interrupt is raised
3. IRQ general purpose interrupt handling
4. Supervisor protected mode for the operating system
entered on reset or software interrupt instruction

5. System Privileged mode using the same registers as user mode

(not in ARM architectures 1, 2 and 3)

6. Abort used to handle memory access violations

7. Undefined used to handle undefined instructions
 Registers (1)
The ARM7 core has 37 registers (32-bits wide)
 General purpose registers
• 1 program counter
• 30 general purpose registers
 Status registers
• 1 current program status register
• 5 saved program status registers
These registers are not all accessible at the same time. The
processor state and operating mode determine which registers are
available to the programmer.
 Registers (II)
 Depending on processor mode one of several banks is
accessible. Each mode can access
• The program counter r15 (PC)
• A particular r13 (stack pointer SP)
• A particular r14 (subroutine link register, LR)
• A set of r0 - r7 registers, and a particular set of r8 – r12
• The current program status register (CPSR)
 Privileged modes (except System mode) can also access
• A particular SPSR (Saved Program Status Register)
 Register Overview
User and system FIQ IRQ Supervisor Abort Undefined
r0 r0 r0 r0 r0 r0
r1 r1 r1 r1 r1 r1
Thumb state Low

r2 r2 r2 r2 r2 r2
r3 r3 r3 r3 r3 r3
r4 r4 r4 r4 r4 r4
registers

r5 r5 r5 r5 r5 r5
r6 r6 r6 r6 r6 r6
r7 r7 r7 r7 r7 r7
------------------------------------------------------------------------------------
r8 r8_fiq r8 r8 r8 r8
r9 r9_fiq r9 r9 r9 r9
r10 r10_fiq r10 r10 r10 r10
Thumb state High

r11 r11_fiq r11 r11 r11 r11

r12 r12_fiq r12 r12 r12 r12
R13(SP) r13_fiq(SP) r13_irq(SP) r13_fiq(SP) r13_abt(SP) r13_und(SP)
registers

R14(LR) r14_fiq(LR) r14_irq (LR) r14_svc(LR) r14_abt(LR) r14_und(LR)

R15(PC) r15(PC) r15(PC) r15(PC) r15(PC) r15(PC)

CPSR CPSR CPSR CPSR CPSR

CPSR
SPSR_fiq SPSR_irq SPSR_svc SPSR_abt SPSR_und
 Registers in Thumb State
 The Thumb state register set is a subset of the ARM state set
The programmer has direct access to:
• Eight general registers r0 – r7
• The program counter PC
• A stack pointer SP
• A link register LR
• The current program status register CPSR
 In Thumb state, the high registers (r8-r12) are not part of the
standard register set. The assembly language programmer has
limited access tp them, but can use them for fast temporary
storage
 Thumb vs. ARM r0
r0
r1
r1
r2
r2
r3
r3
Thumb state
r4
Low registers r4
r5
r5
r6
r6
r7
r7

Thumb state
High registers
r13(SP)
r13(SP)
r14(LR)
r14(LR)
r15(PC)
r15(PC)

CPSR CPSR
SPSR SPSR
 Program Status Register (1)
31 30 29 28 27 24 23 16 15 8 7 6 5 4 0
N Z C V Q J I F T mode

Condition code flags Reserved Control bits

 Condition Code Flags
• N: Negative or less than
• Z: Zero
• C: Carry or borrow or result of the shift operations
• V: Overflow
To not disturb reserved bits, a read – modify – write strategy should
be applied to change PSR bits
 Program Status Register (2)
31 30 29 28 27 24 23 16 15 8 7 6 5 4 0
N Z C V Q J I F T mode

Condition code flags Reserved Control bits

 Interrupt Disable Bits  Mode Bits
• I : IRQ interrupts disable 10000 User
10001 FIQ
• F : FIQ interrupts disable
10010 IRQ
 T Bit 10011 Supervisor
• Thumb mode (when set) 10111 Abort
• ARM mode (when cleared) 11011 Undefined
11111 System
 Program Counter (r15)
 When the processor is executing in ARM state
• All instructions are 32 bits wide
• All instructions must be word aligned
• Bits [31:2] contain the PC, bits [1:0] are Zero
(instructions cannot be halfword or byte aligned)
 When the processor is executing in Thumb state
• All instructions are 1 bits wide
• All instructions must be halfword aligned
• Bits [31:1] contain the PC, bit [0] is zero
(instructions cannot be byte aligned)
 Exception
 Exceptions result whenever the normal flow of a program has
to be halted temporarily, for example to service an interrupt
from a peripheral
 Before attempting to handle an exception, the ARM7TDMI-S
preserves the current processor state so that the original
program can resume when the handler routine has finished
 Exception Handling
 Entering an exception the ARM core
• Saves the address of the next instruction in the appropriate LR
r15 (pc) r14_<mode> (LR)

• Copies the CPSR into the appropriate SPSR

CPSR SPSR_<mode>

• Sets appropriate CPSR bits

8 7 6 5 4 3 2 1 0
 Interrupt disable bits
CSPR: mode
 Mode field bits
 If running in Thumb state, enter ARM state
• Forces PC to fetch next instruction from relevant exception vector
*: all exceptions are handled in ARM state!
 Exception Vectors
 Vector Table

0x1C FIQ
0x18 IRQ
0x14 (Reserved)
0x10 Data Abort
0x0c Prefetch Abort
0x08 Software Interrupt
0x04 Undefined Instruction
0x00 Reset
 Multiple Exceptions
 Exception priorities
• When multiple exceptions arise at the same time, a fixed priority
system determines the order in which they are handled
1. Reset Highest priority
2. Data Abort (data memory access cannot be completed)

3. FIQ

4. IRQ

5. Prefetch Abort (instruction memory access cannot be completed)

6. Undefined Instruction

7. SWI – Software Interrupt (to enter supervisor mode) Lowest priority

 Leaving Exception
 To leave an exception, the exception handler must
• Copy SPSR back into CPSR
SPSR_<mode> CPSR

(automatically restoring also I, F and T)

8 7 6 5 4 3 2 1 0
CSPR:

Control bits
- move contents of current LR minus offset* to PC

r14_<mode> (LR)

- *:varies according to type of exception:2,4 or 8

 Instruction Set

 All instructions are 32 – bits long

 Many instruction execute in a single cycle
 Instructions are conditionally executed
 ARM is a load / store architecture
- via registers => RISC
 Load or store multiple registers in a single instruction
using <register list>
 Conditional Execution
Mnemonic Description
EQ Equal
NE Not equal
CS / HS Carry set / Unsigned higher or same
CC / LO Carry Clear / Unsigned lower
MI Negative
PL Positive or zero
VS Overflow
VC No overflow
HI Unsigned higher
LS Unsigned lower or same
GE Signed greater than or equal
LT Signed less than
GT Signed greater than
LE Signed less than or equal
AL Always (normally omitted
 Thumb Instruction Subset

 Subset of most commonly used 32-bit ARM instructions

• 2 address format: destination register same as one source registers
 Compressed into 16bit wide code
• Improved code density
 Decompressed on execution to full 32-bit instructions
• Transparently
• In real – time
• No performance loss
 ARM code can be combined with Thumb code for maximum flexibility
 Thumb Instructions
ARM instruction set Thumb instruction set
31 0 15 0
Recoding
ARM instruction Thumb instruction
ARM instruction Thumb instruction
ARM instruction Thumb instruction
ARM instruction Thumb instruction
ARM instruction Thumb instruction
ARM instruction Thumb instruction
ARM instruction Thumb instruction
 Thumb Instruction Set (1)

 Branch
• Unconditional  2KBytes
• Conditional  256 Bytes
• Branch with Link  4MBytes (2 Instructions!)
• Branch and Exchange change to ARM state if Rm[0] = 0
• Branch and exchange with link
 Data Processing
• Subset of ARM data processing instructions
• Not conditionally execute (but some update flags)
 Thumb Instruction Set (2)
 Instruction Types
 Load and Store
• Register plus 5-bit (PC, SP plus 8) immediate addressing
• Register plus Register addressing
 Load and Store Multiple
• Load / Store list of registers
• Push / Pop (ARM equivalent: STMDB SP!, <registers>)
 Exception Generating Instructions
• SWI (switch to AR mode and privilaged mode)
• Breakpoint (prefetch abort, with debug monitor)
 Translation of Thumb Instruction
Example: ADD Rd, Rd, #Constant Thumb code
15 0
001 10 Rd 8-bit immediate

Minor op-code Immediat

Major op-code denoting ADD Destination and
source register e value
denoting format 3 instruction
move/compare/add/s
ub/with immidiate
value

1110 00 1 0100 1 0Rd 0Rd 000 8-bit immediate

Always condition code

ARM code
 ARM and Thumb Interworking

 Switch between ARM state and Thumb state using BX instruction

 In ARM state: BX<condition> Rn
 In Thumb state: BX Rn

31 1 0
Rn
N: 0-15
ARM / Thumb
BX selection
0: ARM state

31 1 0 1: Thumb state
Destination
address 0
 ARM7TDMI-S
The ARM7TDMI-S is based on ARM7 core
 3 stage pipeline
 Von Neumann architecture
 CPI ~ 1.9
 T: Thumb instruction set
 D: Includes debug extensions
 M: Enhanced multiplier (32X8) with instructions for 64-bit results
 I: Core has Embedded ICE logic extensions
 S: Fully synthesisable (soft IP)
Instruction Pipeline
 The ARM7TDMI-S core uses a pipeline to increase the speed
of the flow of instructions to the processor. This enables
several operations to take place simultaneously
 The Program Counter (PC points to the instruction being
fetched rather than to the instruction being executed
 During normal operation, while one instruction is being
executed, its successor is being decoded, and a third
instruction is being fetched form memory
 3 - Stage Instruction Pipeline
ARM Thumb

PC PC Fetch Instruction Fetched from Memory

PC – 4 PC – 2 Decode Thumb only: Thumb instruction

decompressed to ARM instruction
Instruction decoded

PC – 8 PC – 4 Execute Registers read from Register Bank,

Shift and ALU operations
performed, Registers written back
to Register Bank
 Optimal Pipelining
 In this example it takes 6 clock cycles to execute 6 instructions
 All operations are on registers (single cycle instructions)
 Clock cycles per instruction(CPI)=1
ADD Fetch Decode Execute
SUB Fetch Decode Execute

MOV Fetch Decode Execute

Fetch Decode Execute
AND
Fetch Decode Execute
ORR
Fetch Decode Execute
EOR
Fetch Decode
CMP
Fetch
RSB

1 2 3 4 5 6 7 8
Cycle
 Branch Pipeline Example

 Branches break the Pipeline

 Example in ARM state
BL 0x8000 Fetch Decode Execute Linkret Adjust
X 0x8004 Fetch Decode
Fetch
X 0x8008
Fetch Decode Execute
ADD 0x8FEc
Fetch Decode Execute
SUB 0x8FF0 Fetch Decode
MOV 0x8FF4 Fetch
AND 0x8FF8

1 2 3 4 5 6 7
Cycle
 Example ARM based System

RAM ARM core

16 bit wide

I/O
Interrupt
Peripherals
Controller

ROM
8 bit wide RAM
32 bit wide
 AMBA
 Advanced Microcontroller Bus Architecture
 On – chip interconnect
 Established, open specification
 Framework for SOC designs
Enabler for IP reuse

 ‘Digital glue’ that binds IP cores together

 Example AMBA System
Keypad
ARM core
UART

High-
bandwidth APB APB
Timer
Memory
AHB Bridge
Interface
Display

High-
RTC
bandwidth on-
DMA Bus
chip RAM Master
I/O
 AHB and APB / VPB
 Advanced High – Performance Bus
• high – performance
• pipelined
• fully – synchronous backplane
• multiple bus masters
 Advanced Peripheral Bus / VLSI Peripheral Bus
• low – power
• non – pipelined
• simple interface
• wait support (VPB)
 Pipeline- Changes for ARM9TDMI

ARM7TDMI
Fetch Decode Execute
ARM
Instruction Fetch Thumb decode Reg Shi AL Reg
ARM Reg.select .rea ft U .wri
decompress d te
CPI:
~1.9

ARM9TDMI

Fetch Decode Execute Memory Write back

ARM or Thumb
Instruction Fetch Instruction decode Shift+ALU Memory Reg.
Reg. Reg. access write
decode read
CPI:
~1.9